#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
+#include <netdev.h>
#define SDRAM_MODE 0x00CD0000
#define SDRAM_CONTROL 0x504F0000
* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
* is something else than 0x00000000.
*/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
- test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
sdram_start(1);
- test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
if (!dramsize)
sdram_start(0);
- test2 = test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+ test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
if (!dramsize) {
sdram_start(1);
- test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+ test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
}
if (test1 > test2) {
pci_mpc5xxx_init(&hose);
}
#endif
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Built in FEC comes first */
+ return pci_eth_init(bis);
+}