do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
}
+void omap3_set_aux_cr_secure(u32 acr)
+{
+ struct emu_hal_params_rx51 emu_romcode_params = { 0, };
+
+ emu_romcode_params.num_params = 2;
+ emu_romcode_params.param1 = acr;
+
+ omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
+ (u32 *)&emu_romcode_params);
+}
+
/*
* Routine: omap3_update_aux_cr_secure_rx51
* Description: Modify the contents Auxiliary Control Register.
*/
static void omap3_update_aux_cr_secure_rx51(u32 set_bits, u32 clear_bits)
{
- struct emu_hal_params_rx51 emu_romcode_params = { 0, };
u32 acr;
/* Read ACR */
asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
acr &= ~clear_bits;
acr |= set_bits;
-
- emu_romcode_params.num_params = 2;
- emu_romcode_params.param1 = acr;
-
- omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
- (u32 *)&emu_romcode_params);
+ omap3_set_aux_cr_secure(acr);
}
/*
/* reuse atags from previous bootloader */
reuse_atags();
- dieid_num_r();
+ omap_die_id_display();
print_cpuinfo();
/*
* Cortex-A8(r1p0..r1p2) errata 430973 workaround
* Set IBE bit in Auxiliary Control Register
+ *
+ * Call this routine only on real secure device
+ * Qemu does not implement secure PPA and crash
*/
- omap3_update_aux_cr_secure_rx51(1 << 6, 0);
+ if (get_device_type() == HS_DEVICE)
+ omap3_update_aux_cr_secure_rx51(1 << 6, 0);
return 0;
}