* Pantelis Antoniou, Intracom S.A., panto@intracom.gr
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
/*
#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU)
/* 8 */
-#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
}
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size;
/*
* Map controller bank 3 to the SDRAM bank at preliminary address.
*/
- memctl->memc_or3 = CFG_OR3_PRELIM;
- memctl->memc_br3 = CFG_BR3_PRELIM;
+ memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+ memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
- memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */
+ memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */
udelay(200);
mii_init();
for (phyno = 0; phyno < 32; ++phyno) {
- fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v);
+ fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v);
if (v == 0xFFFF)
continue;
- fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD);
+ fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN);
udelay(10000);
- fec8xx_miiphy_write(NULL, phyno, PHY_BMCR,
- PHY_BMCR_RESET | PHY_BMCR_AUTON);
+ fec8xx_miiphy_write(NULL, phyno, MII_BMCR,
+ BMCR_RESET | BMCR_ANENABLE);
udelay(10000);
}
}
int board_early_init_f(void)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile iop8xx_t *ioport = &immap->im_ioport;
volatile cpm8xx_t *cpm = &immap->im_cpm;
volatile memctl8xx_t *memctl = &immap->im_memctl;
return 0;
}
-#if defined(CONFIG_CMD_NAND)
-
-#include <linux/mtd/nand_legacy.h>
-
-extern ulong nand_probe(ulong physadr);
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- unsigned long totlen;
-
- totlen = nand_probe(CFG_NAND_BASE);
- printf ("%4lu MB\n", totlen >> 20);
-}
-#endif
-
#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)
#endif
-#ifdef CONFIG_SHOW_ACTIVITY
-
-/* called from timer interrupt every 1/CFG_HZ sec */
-void board_show_activity(ulong timestamp)
-{
-}
-
-/* called when looping */
-void show_activity(int arg)
-{
-}
-
-#endif
-
-#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE)
+#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
int overwrite_console(void)
{
/* printf("overwrite_console called\n"); */
#if CONFIG_NETTA2_VERSION == 2
/* assert peripheral reset */
- ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat &= ~_BW(12);
+ ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~_BW(12);
for (i = 0; i < 10; i++)
udelay(1000);
- ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat |= _BW(12);
+ ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat |= _BW(12);
#endif
reset_phys();