#include <watchdog.h>
#endif
+int fec8xx_miiphy_read(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value);
+int fec8xx_miiphy_write(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value);
+
/****************************************************************/
/* some sane bit macros */
#if defined(CONFIG_NETTA_ISDN)
" with ISDN support"
#endif
+#if defined(CONFIG_NETTA_6412)
+ " (DSP:TI6412)"
+#else
+ " (DSP:TI6711)"
+#endif
"\n"
);
return (0);
}
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
mii_init();
for (phyno = 0; phyno < 32; ++phyno) {
- miiphy_read(phyno, PHY_PHYIDR1, &v);
+ fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v);
if (v == 0xFFFF)
continue;
- miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
+ fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD);
udelay(10000);
- miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
+ fec8xx_miiphy_write(NULL, phyno, PHY_BMCR,
+ PHY_BMCR_RESET | PHY_BMCR_AUTON);
udelay(10000);
}
}
#define PA_SP_DIRVAL 0
#define PB_GP_INMASK (_B(28) | _B(31))
-#define PB_GP_OUTMASK (_BR(16, 19) | _BR(26, 27) | _BR(29, 30))
+#define PB_GP_OUTMASK (_BR(15, 19) | _BR(26, 27) | _BR(29, 30))
#define PB_SP_MASK (_BR(22, 25))
#define PB_ODR_VAL 0
-#define PB_GP_OUTVAL (_BR(16, 19) | _BR(26, 27) | _BR(29, 31))
+#define PB_GP_OUTVAL (_BR(15, 19) | _BR(26, 27) | _BR(29, 31))
#define PB_SP_DIRVAL 0
#define PC_GP_INMASK (_BW(5) | _BW(7) | _BW(8) | _BWR(9, 11) | _BWR(13, 15))
#define PD_GP_INMASK 0
#define PD_GP_OUTMASK _BWR(3, 15)
#define PD_SP_MASK 0
+
+#if defined(CONFIG_NETTA_6412)
+
+#define PD_GP_OUTVAL (_BWR(5, 7) | _BW(9) | _BW(11) | _BW(15))
+
+#else
+
#define PD_GP_OUTVAL (_BWR(5, 7) | _BW(9) | _BW(11))
+
+#endif
+
#define PD_SP_DIRVAL 0
int board_early_init_f(void)
/* CS1: NAND chip select */
memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_SCY_2_CLK | OR_TRLX | OR_ACS_DIV2) ;
memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
-
+#if !defined(CONFIG_NETTA_6412)
/* CS2: DSP */
memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2);
memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
-
+#else
+ /* CS6: DSP */
+ memctl->memc_or6 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2);
+ memctl->memc_br6 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
+#endif
/* CS4: External register chip select */
memctl->memc_or4 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK);
memctl->memc_br4 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
ioport->iop_pddir = PD_GP_OUTMASK | PD_SP_DIRVAL;
ioport->iop_pdpar = PD_SP_MASK;
- ioport->iop_pddat |= (1 << (15 - 6)) | (1 << (15 - 7));
+ /* ioport->iop_pddat |= (1 << (15 - 6)) | (1 << (15 - 7)); */
return 0;
}
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
-#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_legacy.h>
extern ulong nand_probe(ulong physadr);
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
}
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+#if defined(CONFIG_CMD_PCMCIA)
int pcmcia_init(void)
{