*/
#include <common.h>
+#include <asm/io.h>
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if defined(CONFIG_CMD_NAND)
#include <nand.h>
#define MASK_CLE 0x02
#define MASK_ALE 0x04
-static void netstar_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void netstar_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
- switch (cmd) {
- case NAND_CTL_SETCLE: IO_ADDR_W |= MASK_CLE; break;
- case NAND_CTL_SETALE: IO_ADDR_W |= MASK_ALE; break;
+ if (ctrl & NAND_CTRL_CHANGE) {
+ if ( ctrl & NAND_CLE )
+ IO_ADDR_W |= MASK_CLE;
+ if ( ctrl & NAND_ALE )
+ IO_ADDR_W |= MASK_ALE;
}
- this->IO_ADDR_W = (void *) IO_ADDR_W;
-}
+ this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
-/*
- * chip R/B detection
- */
-/***
-static int netstar_nand_ready(struct mtd_info *mtd)
-{
- return (*(volatile ushort *)GPIO_DATA_INPUT_REG) & 0x02;
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
}
-***/
-void board_nand_init(struct nand_chip *nand)
+int board_nand_init(struct nand_chip *nand)
{
nand->options = NAND_SAMSUNG_LP_OPTIONS;
- nand->eccmode = NAND_ECC_SOFT;
- nand->hwcontrol = netstar_nand_hwcontrol;
-/* nand->dev_ready = netstar_nand_ready; */
- nand->chip_delay = 18;
+ nand->ecc.mode = NAND_ECC_SOFT;
+ nand->cmd_ctrl = netstar_nand_hwcontrol;
+ nand->chip_delay = 400;
+ return 0;
}
#endif