}
get_sys_info(&board_cfg);
- printf(", %d MHz", (board_cfg.freqPLB * 2) / 1000000);
+ printf(", %lu MHz", (board_cfg.freqPLB * 2) / 1000000);
mfsdram(DDR0_03, val);
val = DDR0_03_CASLAT_DECODE(val);
/* -----------------------------------------------------------+
* Wait for the DCC master delay line to finish calibration
* ----------------------------------------------------------*/
- mtdcr(memcfga, DDR0_17);
+ mtdcr(SDRAM0_CFGADDR, DDR0_17);
val = DDR0_17_DLLLOCKREG_UNLOCKED;
while (wait != 0xffff) {
- val = mfdcr(memcfgd);
+ val = mfdcr(SDRAM0_CFGDATA);
if ((val & DDR0_17_DLLLOCKREG_MASK) ==
DDR0_17_DLLLOCKREG_LOCKED)
/* dlllockreg bit on */
}
#ifdef CONFIG_DDR_ECC
-static void blank_string(int size)
+void blank_string(int size)
{
int i;
u32 *magicPtr;
u32 magic;
- if ((mfspr(dbcr0) & 0x80000000) == 0) {
+ if ((mfspr(SPRN_DBCR0) & 0x80000000) == 0) {
/* only if no external debugger is alive!
* Check whether vxWorks is using EDR logging, if yes zero
* also PostMortem and user reserved memory
* If not done, then we could get an interrupt later on when
* exceptions are enabled.
*/
- mtspr(mcsr, mfspr(mcsr));
+ mtspr(SPRN_MCSR, mfspr(SPRN_MCSR));
/* Set 'int_mask' parameter to functionnal value */
mfsdram(DDR0_01, val);
* initdram -- 440EPx's DDR controller is a DENALI Core
*
************************************************************************/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
unsigned int dram_size = 0;
/*
* Program tlb entries for this size (dynamic)
*/
- remove_tlb(CFG_SDRAM_BASE, 256 << 20);
+ remove_tlb(CONFIG_SYS_SDRAM_BASE, 256 << 20);
program_tlb(0, 0, dram_size, TLB_WORD2_W_ENABLE | TLB_WORD2_I_ENABLE);
/*
* Setup 2nd TLB with same physical address but different virtual
* address with cache enabled. This is done for fast ECC generation.
*/
- program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0);
+ program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, dram_size, 0);
#ifdef CONFIG_DDR_ECC
/*
* If ECC is enabled, initialize the parity bits.
*/
- program_ecc(CFG_DDR_CACHED_ADDR, dram_size);
+ program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, dram_size);
#endif
return (dram_size);