*
* Mostly copied form atmel ATNGW100 sources
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
-#include "../cpu/at32ap/at32ap700x/sm.h"
-
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/sdram.h>
#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/hmatrix.h>
-#include <asm/arch/memory-map.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/portmux.h>
DECLARE_GLOBAL_DATA_PTR;
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+ {
+ .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
+ .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
+ .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
+ | MMU_VMR_CACHE_NONE,
+ }, {
+ .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
+ .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
+ .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
+ | MMU_VMR_CACHE_WRBACK,
+ },
+};
+
static const struct sdram_config sdram_config = {
.data_bits = SDRAM_DATA_32BIT,
.row_bits = 13,
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
- return macb_eth_initialize(0, (void *)MACB0_BASE, bis->bi_phy_id[0]);
+ return macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0,
+ bis->bi_phy_id[0]);
}
#endif
/* Enable SDRAM in the EBI mux */
hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
- gpio_enable_ebi();
- gpio_enable_usart1();
+ portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
+ sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
+
+ portmux_enable_usart1(PORTMUX_DRIVE_MIN);
#if defined(CONFIG_MACB)
- gpio_enable_macb0();
+ portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
#endif
#if defined(CONFIG_MMC)
- gpio_enable_mmci();
+ portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
#endif
return 0;
}
-phys_size_t initdram(int board_type)
-{
- unsigned long expected_size;
- unsigned long actual_size;
- void *sdram_base;
-
- sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
-
- expected_size = sdram_init(sdram_base, &sdram_config);
- actual_size = get_ram_size(sdram_base, expected_size);
-
- unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
-
- if (expected_size != actual_size)
- printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
- actual_size >> 20, expected_size >> 20);
-
- return actual_size;
-}
-
-void board_init_info(void)
+int board_early_init_r(void)
{
gd->bd->bi_phy_id[0] = 0x01;
+ return 0;
}
-void gclk_init(void)
+int board_postclk_init(void)
{
/* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */
-
- /* Select GCLK3 peripheral function */
- gpio_select_periph_A(GPIO_PIN_PB29, 0);
-
- /* Enable GCLK3 with no input divider, from OSC0 (crystal) */
- sm_writel(PM_GCCTRL(3), SM_BIT(CEN));
+ gclk_enable_output(3, PORTMUX_DRIVE_LOW);
+ gclk_set_rate(3, GCLK_PARENT_OSC0, 25000000);
+ return 0;
}