avr32: fixup definitions to ATMEL_BASE_xxx

[platform/kernel/u-boot.git] / board / miromico / hammerhead / hammerhead.c

diff --git a/board/miromico/hammerhead/hammerhead.c b/board/miromico/hammerhead/hammerhead.c
index d3875f4..911a0b3 100644 (file)
--- a/board/miromico/hammerhead/hammerhead.c
+++ b/board/miromico/hammerhead/hammerhead.c
@@ -22,20 +22,33 @@
  * MA 02111-1307 USA
  */
 
-#include "../cpu/at32ap/at32ap700x/sm.h"
-
 #include <common.h>
 #include <netdev.h>
 
 #include <asm/io.h>
 #include <asm/sdram.h>
 #include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
 #include <asm/arch/hmatrix.h>
-#include <asm/arch/memory-map.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/portmux.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+       {
+               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
+               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+                                       | MMU_VMR_CACHE_NONE,
+       }, {
+               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
+               .nr_pages       = EBI_SDRAM_SIZE >> PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+                                       | MMU_VMR_CACHE_WRBACK,
+       },
+};
+
 static const struct sdram_config sdram_config = {
        .data_bits      = SDRAM_DATA_32BIT,
        .row_bits       = 13,
@@ -55,7 +68,8 @@ static const struct sdram_config sdram_config = {
 #ifdef CONFIG_CMD_NET
 int board_eth_init(bd_t *bis)
 {
-       return macb_eth_initialize(0, (void *)MACB0_BASE, bis->bi_phy_id[0]);
+       return macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0,
+               bis->bi_phy_id[0]);
 }
 #endif
 
@@ -64,14 +78,14 @@ int board_early_init_f(void)
        /* Enable SDRAM in the EBI mux */
        hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
 
-       gpio_enable_ebi();
-       gpio_enable_usart1();
+       portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
+       portmux_enable_usart1(PORTMUX_DRIVE_MIN);
 
 #if defined(CONFIG_MACB)
-       gpio_enable_macb0();
+       portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
 #endif
 #if defined(CONFIG_MMC)
-       gpio_enable_mmci();
+       portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
 #endif
        return 0;
 }
@@ -82,13 +96,11 @@ phys_size_t initdram(int board_type)
        unsigned long actual_size;
        void *sdram_base;
 
-       sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
+       sdram_base = uncached(EBI_SDRAM_BASE);
 
        expected_size = sdram_init(sdram_base, &sdram_config);
        actual_size = get_ram_size(sdram_base, expected_size);
 
-       unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
-
        if (expected_size != actual_size)
                printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
                       actual_size >> 20, expected_size >> 20);
@@ -96,18 +108,16 @@ phys_size_t initdram(int board_type)
        return actual_size;
 }
 
-void board_init_info(void)
+int board_early_init_r(void)
 {
        gd->bd->bi_phy_id[0] = 0x01;
+       return 0;
 }
 
-void gclk_init(void)
+int board_postclk_init(void)
 {
        /* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */
-
-       /* Select GCLK3 peripheral function */
-       gpio_select_periph_A(GPIO_PIN_PB29, 0);
-
-       /* Enable GCLK3 with no input divider, from OSC0 (crystal) */
-       sm_writel(PM_GCCTRL(3), SM_BIT(CEN));
+       gclk_enable_output(3, PORTMUX_DRIVE_LOW);
+       gclk_set_rate(3, GCLK_PARENT_OSC0, 25000000);
+       return 0;
 }