Merge with /home/stefan/git/u-boot/u-boot-ppc4xx

[platform/kernel/u-boot.git] / board / lwmon5 / sdram.c

diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c
index 85811ad..d4547e2 100644 (file)
--- a/board/lwmon5/sdram.c
+++ b/board/lwmon5/sdram.c
@@ -54,11 +54,9 @@
 #define MY_TLB_WORD2_I_ENABLE  TLB_WORD2_I_ENABLE      /* disable caching on SDRAM */
 #endif
 
-void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
 void dcbz_area(u32 start_address, u32 num_bytes);
 void dflush(void);
 
-#ifdef CONFIG_ADD_RAM_INFO
 static u32 is_ecc_enabled(void)
 {
        u32 val;
@@ -88,7 +86,6 @@ void board_add_ram_info(int use_default)
        val = DDR0_03_CASLAT_DECODE(val);
        printf(", CL%d)", val);
 }
-#endif
 
 static int wait_for_dlllock(void)
 {
@@ -474,8 +471,32 @@ static void program_ecc(u32 start_address,
                blank_string(strlen(str));
        } else {
                /* ECC bit set method for cached memory */
+#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
+               /*
+                * Some boards (like lwmon5) need to preserve the memory
+                * content upon ECC generation (for the log-buffer).
+                * Therefore we don't fill the memory with a pattern or
+                * just zero it, but write the same values back that are
+                * already in the memory cells.
+                */
+               address_increment = CFG_CACHELINE_SIZE;
+               end_address = current_address + num_bytes;
+
+               current_address = start_address;
+               while (current_address < end_address) {
+                       /*
+                        * TODO: Th following sequence doesn't work correctly.
+                        * Just invalidating and flushing the cache doesn't
+                        * seem to trigger the re-write of the memory.
+                        */
+                       ppcDcbi(current_address);
+                       ppcDcbf(current_address);
+                       current_address += CFG_CACHELINE_SIZE;
+               }
+#else
                dcbz_area(start_address, num_bytes);
                dflush();
+#endif
        }
 
        sync();
@@ -496,19 +517,6 @@ static void program_ecc(u32 start_address,
 }
 #endif
 
-static __inline__ u32 get_mcsr(void)
-{
-       u32 val;
-
-       asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
-       return val;
-}
-
-static __inline__ void set_mcsr(u32 val)
-{
-       asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
-}
-
 /*************************************************************************
  *
  * initdram -- 440EPx's DDR controller is a DENALI Core
@@ -516,8 +524,8 @@ static __inline__ void set_mcsr(u32 val)
  ************************************************************************/
 long int initdram (int board_type)
 {
-       u32 val;
-
+#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
+       /* CL=3 */
        mtsdram(DDR0_02, 0x00000000);
 
        mtsdram(DDR0_00, 0x0000190A);
@@ -558,6 +566,49 @@ long int initdram (int board_type)
        mtsdram(DDR0_43, 0x030A0200);
        mtsdram(DDR0_44, 0x00000003);
        mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
+#else
+       /* CL=4 */
+       mtsdram(DDR0_02, 0x00000000);
+
+       mtsdram(DDR0_00, 0x0000190A);
+       mtsdram(DDR0_01, 0x01000000);
+       mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */
+
+       mtsdram(DDR0_04, 0x0B030300);
+       mtsdram(DDR0_05, 0x02020308);
+       mtsdram(DDR0_06, 0x0003C812);
+       mtsdram(DDR0_07, 0x00090100);
+       mtsdram(DDR0_08, 0x03c80001);
+       mtsdram(DDR0_09, 0x00011D5F);
+       mtsdram(DDR0_10, 0x00000300);
+       mtsdram(DDR0_11, 0x000CC800);
+       mtsdram(DDR0_12, 0x00000003);
+       mtsdram(DDR0_14, 0x00000000);
+       mtsdram(DDR0_17, 0x1e000000);
+       mtsdram(DDR0_18, 0x1e1e1e1e);
+       mtsdram(DDR0_19, 0x1e1e1e1e);
+       mtsdram(DDR0_20, 0x0B0B0B0B);
+       mtsdram(DDR0_21, 0x0B0B0B0B);
+#ifdef CONFIG_DDR_ECC
+       mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC       */
+#else
+       mtsdram(DDR0_22, 0x00267F0B);
+#endif
+
+       mtsdram(DDR0_23, 0x01000000);
+       mtsdram(DDR0_24, 0x01010001);
+
+       mtsdram(DDR0_26, 0x2D93028A);
+       mtsdram(DDR0_27, 0x0784682B);
+
+       mtsdram(DDR0_28, 0x00000080);
+       mtsdram(DDR0_31, 0x00000000);
+       mtsdram(DDR0_42, 0x01000008);
+
+       mtsdram(DDR0_43, 0x050A0200);
+       mtsdram(DDR0_44, 0x00000005);
+       mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
+#endif
 
        wait_for_dlllock();
 
@@ -577,14 +628,6 @@ long int initdram (int board_type)
         * Perform data eye search if requested.
         */
        denali_core_search_data_eye(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20);
-
-       /*
-        * Clear possible errors resulting from data-eye-search.
-        * If not done, then we could get an interrupt later on when
-        * exceptions are enabled.
-        */
-       val = get_mcsr();
-       set_mcsr(val);
 #endif
 
 #ifdef CONFIG_DDR_ECC
@@ -594,5 +637,12 @@ long int initdram (int board_type)
        program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
 #endif
 
+       /*
+        * Clear possible errors resulting from data-eye-search.
+        * If not done, then we could get an interrupt later on when
+        * exceptions are enabled.
+        */
+       set_mcsr(get_mcsr());
+
        return (CFG_MBYTES_SDRAM << 20);
 }