gpio_write_bit(CFG_GPIO_FLASH_WP, 1);
+#if CONFIG_POST & CFG_POST_BSPEC1
+ gpio_write_bit(CFG_GPIO_HIGHSIDE, 1);
+
+ reg = 0; /* reuse as counter */
+ out_be32((void *)CFG_DSPIC_TEST_ADDR,
+ in_be32((void *)CFG_DSPIC_TEST_ADDR)
+ & ~CFG_DSPIC_TEST_MASK);
+ while (!gpio_read_in_bit(CFG_GPIO_DSPIC_READY) && reg++ < 1000) {
+ udelay(1000);
+ }
+ gpio_write_bit(CFG_GPIO_HIGHSIDE, 0);
+ if (gpio_read_in_bit(CFG_GPIO_DSPIC_READY)) {
+ /* set "boot error" flag */
+ out_be32((void *)CFG_DSPIC_TEST_ADDR,
+ in_be32((void *)CFG_DSPIC_TEST_ADDR) |
+ CFG_DSPIC_TEST_MASK);
+ }
+#endif
+
/*
* Reset PHY's:
* The PHY's need a 2nd reset pulse, since the MDIO address is latched
/* Env protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
- CFG_ENV_ADDR_REDUND,
- CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
+ CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
&flash_info[1]);
/*
return (0);
}
-#if defined(CFG_DRAM_TEST)
-int testdram(void)
-{
- unsigned long *mem = (unsigned long *)0;
- const unsigned long kend = (1024 / sizeof(unsigned long));
- unsigned long k, n;
-
- mtmsr(0);
-
- for (k = 0; k < CFG_MBYTES_SDRAM;
- ++k, mem += (1024 / sizeof(unsigned long))) {
- if ((k & 1023) == 0) {
- printf("%3d MB\r", k / 1024);
- }
-
- memset(mem, 0xaaaaaaaa, 1024);
- for (n = 0; n < kend; ++n) {
- if (mem[n] != 0xaaaaaaaa) {
- printf("SDRAM test fails at: %08x\n",
- (uint) & mem[n]);
- return 1;
- }
- }
-
- memset(mem, 0x55555555, 1024);
- for (n = 0; n < kend; ++n) {
- if (mem[n] != 0x55555555) {
- printf("SDRAM test fails at: %08x\n",
- (uint) & mem[n]);
- return 1;
- }
- }
- }
- printf("SDRAM test passes\n");
- return 0;
-}
-#endif
-
/*************************************************************************
* pci_pre_init
*
void hw_watchdog_reset(void)
{
int val;
+#if defined(CONFIG_WD_MAX_RATE)
+ unsigned long long ct = get_ticks();
+
+ /*
+ * Don't allow watch-dog triggering more frequently than
+ * the predefined value CONFIG_WD_MAX_RATE [ticks].
+ */
+ if (ct >= gd->wdt_last) {
+ if ((ct - gd->wdt_last) < CONFIG_WD_MAX_RATE)
+ return;
+ } else {
+ /* Time base counter had been reset */
+ if (((unsigned long long)(-1) - gd->wdt_last + ct) <
+ CONFIG_WD_MAX_RATE)
+ return;
+ }
+ gd->wdt_last = get_ticks();
+#endif
/*
* Toggle watchdog output
return CFG_LIME_BASE_0;
}
-void board_backlight_switch (int flag)
+#define DEFAULT_BRIGHTNESS 0x64
+
+static void board_backlight_brightness(int brightness)
{
- if (flag) {
+ if (brightness > 0) {
/* pwm duty, lamp on */
- out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000024), 0x64);
+ out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000024), brightness);
out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000020), 0x701);
} else {
/* lamp off */
}
}
+void board_backlight_switch (int flag)
+{
+ char * param;
+ int rc;
+
+ if (flag) {
+ param = getenv("brightness");
+ rc = param ? simple_strtol(param, NULL, 10) : -1;
+ if (rc < 0)
+ rc = DEFAULT_BRIGHTNESS;
+ } else {
+ rc = 0;
+ }
+ board_backlight_brightness(rc);
+}
+
#if defined(CONFIG_CONSOLE_EXTRA_INFO)
/*
* Return text to be printed besides the logo.
}
#endif
#endif /* CONFIG_VIDEO */
+
+void board_reset(void)
+{
+ gpio_write_bit(CFG_GPIO_BOARD_RESET, 1);
+}