#define ZL30158_RST 8
-#define ZL30343_RST 9
+#define BFTIC4_RST 0
+#define RSTRQSR1_WDT_RR 0x00200000
+#define RSTRQSR1_SW_RR 0x00100000
int board_early_init_f(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ bool cpuwd_flag = false;
+
+ /* configure mode for uP reset request */
+ qrio_uprstreq(UPREQ_CORE_RST);
/* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
setbits_be32(&gur->ddrclkdr, 0x001f000f);
- /* take the Zarlinks out of reset as soon as possible */
- qrio_prst(ZL30158_RST, false, false);
- qrio_prst(ZL30343_RST, false, false);
+ /* set reset reason according CPU register */
+ if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
+ RSTRQSR1_WDT_RR)
+ cpuwd_flag = true;
+
+ qrio_cpuwd_flag(cpuwd_flag);
+ /* clear CPU bits by writing 1 */
+ setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
- /* and set their reset to power-up only */
- qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);
- qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
+ /* set the BFTIC's prstcfg to reset at power-up and unit reset only */
+ qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
+ /* and enable WD on it */
+ qrio_wdmask(BFTIC4_RST, true);
+
+ /* set the ZL30138's prstcfg to reset at power-up and unit reset only */
+ qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_UNIT_RST);
+ /* and take it out of reset as soon as possible (needed for Hooper) */
+ qrio_prst(ZL30158_RST, false, false);
return 0;
}
return 66666666;
}
+#define ETH_FRONT_PHY_RST 15
+#define QSFP2_RST 11
+#define QSFP1_RST 10
+#define ZL30343_RST 9
+
int misc_init_f(void)
{
/* configure QRIO pis for i2c deblocking */
i2c_deblock_gpio_cfg();
+ /* configure the front phy's prstcfg and take it out of reset */
+ qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+ qrio_prst(ETH_FRONT_PHY_RST, false, false);
+
+ /* set the ZL30343 prstcfg to reset at power-up and unit reset only */
+ qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_UNIT_RST);
+ /* and enable the WD on it */
+ qrio_wdmask(ZL30343_RST, true);
+
+ /* set the QSFPs' prstcfg to reset at power-up and unit rst only */
+ qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST);
+
+ /* and enable the WD on them */
+ qrio_wdmask(QSFP1_RST, true);
+ qrio_wdmask(QSFP2_RST, true);
+
return 0;
}
#define NUM_SRDS_BANKS 2
-#define PHY_RST 15
int misc_init_r(void)
{
}
}
- /* take the mgmt eth phy out of reset */
- qrio_prst(PHY_RST, false, false);
-
return 0;
}
#endif
#if defined(CONFIG_LAST_STAGE_INIT)
+
int last_stage_init(void)
{
#if defined(CONFIG_KMCOGE4)
}
#endif
set_km_env();
+
return 0;
}
#endif
fdt_fixup_fman_mac_addresses(blob);
#endif
}
+
+#if defined(CONFIG_POST)
+
+/* DIC26_SELFTEST GPIO used to start factory test sw */
+#define SELFTEST_PORT GPIO_A
+#define SELFTEST_PIN 31
+
+int post_hotkeys_pressed(void)
+{
+ qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
+ return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
+}
+#endif