return 0;
}
-/* TODO: implement the I2C deblocking function */
-int i2c_make_abort(void)
+/* I2C deblocking uses the algorithm defined in board/keymile/common/common.c
+ * 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines
+ * For I2C only the low state is activly driven and high state is pulled-up
+ * by a resistor. Therefore the deblock GPIOs are used
+ * -> as an active output to drive a low state
+ * -> as an open-drain input to have a pulled-up high state
+ */
+
+/* QRIO GPIOs used for deblocking */
+#define DEBLOCK_PORT1 GPIO_A
+#define DEBLOCK_SCL1 20
+#define DEBLOCK_SDA1 21
+
+/* By default deblock GPIOs are floating */
+static void i2c_deblock_gpio_cfg(void)
+{
+ /* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */
+ qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SCL1);
+ qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SDA1);
+
+ qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, 0);
+ qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, 0);
+}
+
+void set_sda(int state)
+{
+ qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, state);
+}
+
+void set_scl(int state)
+{
+ qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, state);
+}
+
+int get_sda(void)
{
- return 1;
+ return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1);
}
+int get_scl(void)
+{
+ return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1);
+}
+
+
#define ZL30158_RST 8
-#define ZL30343_RST 9
+#define BFTIC4_RST 0
+#define RSTRQSR1_WDT_RR 0x00200000
+#define RSTRQSR1_SW_RR 0x00100000
int board_early_init_f(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ bool cpuwd_flag = false;
+
+ /* configure mode for uP reset request */
+ qrio_uprstreq(UPREQ_CORE_RST);
/* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
setbits_be32(&gur->ddrclkdr, 0x001f000f);
- /* take the Zarlinks out of reset as soon as possible */
- qrio_prst(ZL30158_RST, false, false);
- qrio_prst(ZL30343_RST, false, false);
+ /* set reset reason according CPU register */
+ if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
+ RSTRQSR1_WDT_RR)
+ cpuwd_flag = true;
+
+ qrio_cpuwd_flag(cpuwd_flag);
+ /* clear CPU bits by writing 1 */
+ setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
- /* and set their reset to power-up only */
- qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);
- qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
+ /* set the BFTIC's prstcfg to reset at power-up and unit reset only */
+ qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
+ /* and enable WD on it */
+ qrio_wdmask(BFTIC4_RST, true);
+
+ /* set the ZL30138's prstcfg to reset at power-up and unit reset only */
+ qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_UNIT_RST);
+ /* and take it out of reset as soon as possible (needed for Hooper) */
+ qrio_prst(ZL30158_RST, false, false);
return 0;
}
int board_early_init_r(void)
{
+ int ret = 0;
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
set_liodns();
setup_portals();
- return 0;
+ ret = trigger_fpga_config();
+ if (ret)
+ printf("error triggering PCIe FPGA config\n");
+
+ /* enable the Unit LED (red) & Boot LED (on) */
+ qrio_set_leds();
+
+ /* enable Application Buffer */
+ qrio_enable_app_buffer();
+
+ return ret;
}
unsigned long get_board_sys_clk(unsigned long dummy)
return 66666666;
}
-#define WDMASK_OFF 0x16
+#define ETH_FRONT_PHY_RST 15
+#define QSFP2_RST 11
+#define QSFP1_RST 10
+#define ZL30343_RST 9
-static void qrio_wdmask(u8 bit, bool wden)
+int misc_init_f(void)
{
- u16 wdmask;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+ /* configure QRIO pis for i2c deblocking */
+ i2c_deblock_gpio_cfg();
- wdmask = in_be16(qrio_base + WDMASK_OFF);
+ /* configure the front phy's prstcfg and take it out of reset */
+ qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+ qrio_prst(ETH_FRONT_PHY_RST, false, false);
- if (wden)
- wdmask |= (1 << bit);
- else
- wdmask &= ~(1 << bit);
+ /* set the ZL30343 prstcfg to reset at power-up and unit reset only */
+ qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_UNIT_RST);
+ /* and enable the WD on it */
+ qrio_wdmask(ZL30343_RST, true);
- out_be16(qrio_base + WDMASK_OFF, wdmask);
-}
-
-#define PRST_OFF 0x1a
-
-void qrio_prst(u8 bit, bool en, bool wden)
-{
- u16 prst;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
-
- qrio_wdmask(bit, wden);
-
- prst = in_be16(qrio_base + PRST_OFF);
-
- if (en)
- prst &= ~(1 << bit);
- else
- prst |= (1 << bit);
-
- out_be16(qrio_base + PRST_OFF, prst);
-}
-
-#define PRSTCFG_OFF 0x1c
-
-void qrio_prstcfg(u8 bit, u8 mode)
-{
- u32 prstcfg;
- u8 i;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
-
- prstcfg = in_be32(qrio_base + PRSTCFG_OFF);
+ /* set the QSFPs' prstcfg to reset at power-up and unit rst only */
+ qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST);
- for (i = 0; i < 2; i++) {
- if (mode & (1<<i))
- set_bit(2*bit+i, &prstcfg);
- else
- clear_bit(2*bit+i, &prstcfg);
- }
+ /* and enable the WD on them */
+ qrio_wdmask(QSFP1_RST, true);
+ qrio_wdmask(QSFP2_RST, true);
- out_be32(qrio_base + PRSTCFG_OFF, prstcfg);
+ return 0;
}
#define NUM_SRDS_BANKS 2
-#define PHY_RST 15
int misc_init_r(void)
{
}
}
- /* take the mgmt eth phy out of reset */
- qrio_prst(PHY_RST, false, false);
-
return 0;
}
#endif
#if defined(CONFIG_LAST_STAGE_INIT)
+
int last_stage_init(void)
{
+#if defined(CONFIG_KMCOGE4)
+ /* on KMCOGE4, the BFTIC4 is on the LBAPP2 */
+ struct bfticu_iomap *bftic4 =
+ (struct bfticu_iomap *)CONFIG_SYS_LBAPP2_BASE;
+ u8 dip_switch = in_8((u8 *)&(bftic4->mswitch)) & BFTICU_DIPSWITCH_MASK;
+
+ if (dip_switch != 0) {
+ /* start bootloader */
+ puts("DIP: Enabled\n");
+ setenv("actual_bank", "0");
+ }
+#endif
set_km_env();
+
return 0;
}
#endif
fdt_fixup_fman_mac_addresses(blob);
#endif
}
+
+#if defined(CONFIG_POST)
+
+/* DIC26_SELFTEST GPIO used to start factory test sw */
+#define SELFTEST_PORT GPIO_A
+#define SELFTEST_PIN 31
+
+int post_hotkeys_pressed(void)
+{
+ qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
+ return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
+}
+#endif