Merge branch 'master' of git://git.denx.de/u-boot-arm

[platform/kernel/u-boot.git] / board / keymile / km_arm / fpga_config.c

diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c
index 4356b9a..51a3cfe 100644 (file)
--- a/board/keymile/km_arm/fpga_config.c
+++ b/board/keymile/km_arm/fpga_config.c
@@ -2,23 +2,7 @@
  * (C) Copyright 2012
  * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -96,12 +80,43 @@ static int boco_set_bits(u8 reg, u8 flags)
 #define SPI_REG                0x06
 #define CFG_EEPROM     0x02
 #define FPGA_PROG      0x04
+#define FPGA_INIT_B    0x10
 #define FPGA_DONE      0x20
 
+static int fpga_done(void)
+{
+       int ret = 0;
+       u8 regval;
+
+       /* this is only supported with the boco2 design */
+       if (!check_boco2())
+               return 0;
+
+       ret = i2c_read(BOCO_ADDR, SPI_REG, 1, &regval, 1);
+       if (ret) {
+               printf("%s: error reading the BOCO @%#x !!\n",
+                       __func__, SPI_REG);
+               return 0;
+       }
+
+       return regval & FPGA_DONE ? 1 : 0;
+}
+
+int skip;
+
 int trigger_fpga_config(void)
 {
        int ret = 0;
 
+       /* if the FPGA is already configured, we do not want to
+        * reconfigure it */
+       skip = 0;
+       if (fpga_done()) {
+               printf("PCIe FPGA config: skipped\n");
+               skip = 1;
+               return 0;
+       }
+
        if (check_boco2()) {
                /* we have a BOCO2, this has to be triggered here */
 
@@ -111,7 +126,7 @@ int trigger_fpga_config(void)
                        return ret;
 
                /* trigger the config start */
-               ret = boco_clear_bits(SPI_REG, FPGA_PROG);
+               ret = boco_clear_bits(SPI_REG, FPGA_PROG | FPGA_INIT_B);
                if (ret)
                        return ret;
 
@@ -123,6 +138,11 @@ int trigger_fpga_config(void)
                if (ret)
                        return ret;
 
+               /* finally, raise INIT_B to remove the config delay */
+               ret = boco_set_bits(SPI_REG, FPGA_INIT_B);
+               if (ret)
+                       return ret;
+
        } else {
                /* we do it the old way, with the gpio pin */
                kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1);
@@ -141,6 +161,9 @@ int wait_for_fpga_config(void)
        u8 spictrl;
        u32 timeout = 20000;
 
+       if (skip)
+               return 0;
+
        if (!check_boco2()) {
                /* we do not have BOCO2, this is not really used */
                return 0;
@@ -166,31 +189,62 @@ int wait_for_fpga_config(void)
        return 0;
 }
 
+#if defined(KM_PCIE_RESET_MPP7)
+
+#define KM_PEX_RST_GPIO_PIN    7
+int fpga_reset(void)
+{
+       if (!check_boco2()) {
+               /* we do not have BOCO2, this is not really used */
+               return 0;
+       }
+
+       printf("PCIe reset through GPIO7: ");
+       /* apply PCIe reset via GPIO */
+       kw_gpio_set_valid(KM_PEX_RST_GPIO_PIN, 1);
+       kw_gpio_direction_output(KM_PEX_RST_GPIO_PIN, 1);
+       kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 0);
+       udelay(1000*10);
+       kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 1);
+
+       printf(" done\n");
+
+       return 0;
+}
+
+#else
+
 #define PRST1          0x4
-#define BRIDGE_RST     0x4
+#define PCIE_RST       0x10
+#define TRAFFIC_RST    0x04
 
 int fpga_reset(void)
 {
        int ret = 0;
+       u8 resets;
 
        if (!check_boco2()) {
                /* we do not have BOCO2, this is not really used */
                return 0;
        }
 
-       ret = boco_clear_bits(PRST1, BRIDGE_RST);
+       /* if we have skipped, we only want to reset the PCIe part */
+       resets = skip ? PCIE_RST : PCIE_RST | TRAFFIC_RST;
+
+       ret = boco_clear_bits(PRST1, resets);
        if (ret)
                return ret;
 
        /* small delay for the pulse */
        udelay(10);
 
-       ret = boco_set_bits(PRST1, BRIDGE_RST);
+       ret = boco_set_bits(PRST1, resets);
        if (ret)
                return ret;
 
        return 0;
 }
+#endif
 
 /* the FPGA was configured, we configure the BOCO2 so that the EEPROM
  * is available from the Bobcat SPI bus */
@@ -209,4 +263,3 @@ int toggle_eeprom_spi_bus(void)
 
        return 0;
 }
-