odroid: remove CONFIG_DM_I2C_COMPAT config

[platform/kernel/u-boot.git] / board / keymile / km82xx / km82xx.c

diff --git a/board/keymile/km82xx/km82xx.c b/board/keymile/km82xx/km82xx.c
index bf84676..f5a98b3 100644 (file)
--- a/board/keymile/km82xx/km82xx.c
+++ b/board/keymile/km82xx/km82xx.c
@@ -11,13 +11,14 @@
 #include <malloc.h>
 #include <asm/io.h>
 
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
-#endif
-
 #include <i2c.h>
 #include "../common/common.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
+static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
+
 /*
  * I/O Port configuration table
  *
@@ -152,13 +153,8 @@ const iop_conf_t iop_conf_tab[4][32] = {
                { 0,             0,   0,   0,   0,   0 }, /* PD18            */
                { 0,             0,   0,   0,   0,   0 }, /* PD17            */
                { 0,             0,   0,   0,   0,   0 }, /* PD16            */
-#if defined(CONFIG_HARD_I2C)
-               { 1,             1,   1,   0,   1,   0 }, /* PD15 I2C SDA    */
-               { 1,             1,   1,   0,   1,   0 }, /* PD14 I2C SCL    */
-#else
                { 1,             0,   0,   0,   1,   1 }, /* PD15            */
                { 1,             0,   0,   1,   1,   1 }, /* PD14            */
-#endif
                { 0,             0,   0,   0,   0,   0 }, /* PD13            */
                { 0,             0,   0,   0,   0,   0 }, /* PD12            */
                { 0,             0,   0,   0,   0,   0 }, /* PD11            */
@@ -290,7 +286,7 @@ static long probe_sdram(memctl8260_t *memctl)
 #endif /* CONFIG_SYS_SDRAM_LIST */
 
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
        immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
        memctl8260_t *memctl = &immap->im_memctl;
@@ -306,7 +302,9 @@ phys_size_t initdram(int board_type)
 
        icache_enable();
 
-       return psize;
+       gd->ram_size = psize;
+
+       return 0;
 }
 
 int checkboard(void)
@@ -330,8 +328,8 @@ int last_stage_init(void)
 
        dip_switch = in_8(&base->mswitch);
        dip_switch &= BFTICU_DIPSWITCH_MASK;
-       /* dip switch 'full reset' or 'db erase' */
-       if (dip_switch & 0x1 || dip_switch & 0x2) {
+       /* dip switch 'full reset' or 'db erase' or 'Local mgmt IP' or any */
+       if (dip_switch != 0) {
                /* start bootloader */
                puts("DIP:   Enabled\n");
                setenv("actual_bank", "0");
@@ -341,7 +339,7 @@ int last_stage_init(void)
 }
 
 #ifdef CONFIG_MGCOGE3NE
-static void set_pin(int state, unsigned long mask);
+static void set_pin(int state, unsigned long mask, int port);
 
 /*
  * For mgcoge3ne boards, the mgcoge3un control is controlled from
@@ -355,11 +353,11 @@ static void handle_mgcoge3un_reset(void)
        if (bobcatreset) {
                if (strcmp(bobcatreset, "true") == 0) {
                        puts("Forcing bobcat reset\n");
-                       set_pin(0, 0x00000004); /* clear PD29 to reset arm */
+                       set_pin(0, 0x00000004, 3); /* clear PD29 (reset arm) */
                        udelay(1000);
-                       set_pin(1, 0x00000004);
+                       set_pin(1, 0x00000004, 3);
                } else
-                       set_pin(1, 0x00000004); /* set PD29 to not reset arm */
+                       set_pin(1, 0x00000004, 3); /* don't reset arm */
        }
 }
 #endif
@@ -393,18 +391,24 @@ int board_early_init_r(void)
        return 0;
 }
 
+int misc_init_r(void)
+{
+       ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+       return 0;
+}
+
 int hush_init_var(void)
 {
-       ivm_read_eeprom();
+       ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
        return 0;
 }
 
 #define SDA_MASK       0x00010000
 #define SCL_MASK       0x00020000
 
-static void set_pin(int state, unsigned long mask)
+static void set_pin(int state, unsigned long mask, int port)
 {
-       ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
+       ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, port);
 
        if (state)
                setbits_be32(&iop->pdat, mask);
@@ -414,9 +418,9 @@ static void set_pin(int state, unsigned long mask)
        setbits_be32(&iop->pdir, mask);
 }
 
-static int get_pin(unsigned long mask)
+static int get_pin(unsigned long mask, int port)
 {
-       ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
+       ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, port);
 
        clrbits_be32(&iop->pdir, mask);
        return 0 != (in_be32(&iop->pdat) & mask);
@@ -424,44 +428,36 @@ static int get_pin(unsigned long mask)
 
 void set_sda(int state)
 {
-       set_pin(state, SDA_MASK);
+       set_pin(state, SDA_MASK, 3);
 }
 
 void set_scl(int state)
 {
-       set_pin(state, SCL_MASK);
+       set_pin(state, SCL_MASK, 3);
 }
 
 int get_sda(void)
 {
-       return get_pin(SDA_MASK);
+       return get_pin(SDA_MASK, 3);
 }
 
 int get_scl(void)
 {
-       return get_pin(SCL_MASK);
+       return get_pin(SCL_MASK, 3);
 }
 
-#if defined(CONFIG_HARD_I2C)
-static void setports(int gpio)
-{
-       ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
-
-       if (gpio) {
-               clrbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
-               clrbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
-       } else {
-               setbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
-               clrbits_be32(&iop->pdir, (SDA_MASK | SCL_MASK));
-               setbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
-       }
-}
-#endif
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
 int ft_board_setup(void *blob, bd_t *bd)
 {
        ft_cpu_setup(blob, bd);
 
        return 0;
 }
-#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
+
+#if defined(CONFIG_MGCOGE3NE)
+int get_testpin(void)
+{
+       /* Testpin is Port C pin 29 - enable = low */
+       int testpin = !get_pin(0x00000004, 2);
+       return testpin;
+}
+#endif