* (C) Copyright 2007 - 2008
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <malloc.h>
#include <asm/io.h>
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
-#endif
-
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
#include <i2c.h>
-#endif
-
#include "../common/common.h"
+DECLARE_GLOBAL_DATA_PTR;
+
+static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
+
/*
* I/O Port configuration table
*
{ 0, 0, 0, 0, 0, 0 }, /* PD18 */
{ 0, 0, 0, 0, 0, 0 }, /* PD17 */
{ 0, 0, 0, 0, 0, 0 }, /* PD16 */
-#if defined(CONFIG_HARD_I2C)
- { 1, 1, 1, 0, 1, 0 }, /* PD15 I2C SDA */
- { 1, 1, 1, 0, 1, 0 }, /* PD14 I2C SCL */
-#else
{ 1, 0, 0, 0, 1, 1 }, /* PD15 */
{ 1, 0, 0, 1, 1, 1 }, /* PD14 */
-#endif
{ 0, 0, 0, 0, 0, 0 }, /* PD13 */
{ 0, 0, 0, 0, 0, 0 }, /* PD12 */
{ 0, 0, 0, 0, 0, 0 }, /* PD11 */
#endif /* CONFIG_SYS_SDRAM_LIST */
-phys_size_t initdram(int board_type)
+int dram_init(void)
{
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
memctl8260_t *memctl = &immap->im_memctl;
out_8(&memctl->memc_psrt, CONFIG_SYS_PSRT);
out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
-#ifndef CONFIG_SYS_RAMBOOT
/* 60x SDRAM setup:
*/
psize = probe_sdram(memctl);
-#endif /* CONFIG_SYS_RAMBOOT */
icache_enable();
- return psize;
+ gd->ram_size = psize;
+
+ return 0;
}
int checkboard(void)
dip_switch = in_8(&base->mswitch);
dip_switch &= BFTICU_DIPSWITCH_MASK;
- /* dip switch 'full reset' or 'db erase' */
- if (dip_switch & 0x1 || dip_switch & 0x2) {
+ /* dip switch 'full reset' or 'db erase' or 'Local mgmt IP' or any */
+ if (dip_switch != 0) {
/* start bootloader */
puts("DIP: Enabled\n");
setenv("actual_bank", "0");
}
#ifdef CONFIG_MGCOGE3NE
-static void set_pin(int state, unsigned long mask);
+static void set_pin(int state, unsigned long mask, int port);
/*
* For mgcoge3ne boards, the mgcoge3un control is controlled from
* will toggle once what forces the mgocge3un part to restart
* immediately.
*/
-void handle_mgcoge3un_reset(void)
+static void handle_mgcoge3un_reset(void)
{
char *bobcatreset = getenv("bobcatreset");
if (bobcatreset) {
if (strcmp(bobcatreset, "true") == 0) {
puts("Forcing bobcat reset\n");
- set_pin(0, 0x00000004); /* clear PD29 to reset arm */
+ set_pin(0, 0x00000004, 3); /* clear PD29 (reset arm) */
udelay(1000);
- set_pin(1, 0x00000004);
+ set_pin(1, 0x00000004, 3);
} else
- set_pin(1, 0x00000004); /* set PD29 to not reset arm */
+ set_pin(1, 0x00000004, 3); /* don't reset arm */
}
}
#endif
+int ethernet_present(void)
+{
+ struct km_bec_fpga *base =
+ (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
+
+ return in_8(&base->bprth) & PIGGY_PRESENT;
+}
+
/*
* Early board initalization.
*/
return 0;
}
+int misc_init_r(void)
+{
+ ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+ return 0;
+}
+
int hush_init_var(void)
{
- ivm_read_eeprom();
+ ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
return 0;
}
#define SDA_MASK 0x00010000
#define SCL_MASK 0x00020000
-static void set_pin(int state, unsigned long mask)
+static void set_pin(int state, unsigned long mask, int port)
{
- ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
+ ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, port);
if (state)
setbits_be32(&iop->pdat, mask);
setbits_be32(&iop->pdir, mask);
}
-static int get_pin(unsigned long mask)
+static int get_pin(unsigned long mask, int port)
{
- ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
+ ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, port);
clrbits_be32(&iop->pdir, mask);
return 0 != (in_be32(&iop->pdat) & mask);
void set_sda(int state)
{
- set_pin(state, SDA_MASK);
+ set_pin(state, SDA_MASK, 3);
}
void set_scl(int state)
{
- set_pin(state, SCL_MASK);
+ set_pin(state, SCL_MASK, 3);
}
int get_sda(void)
{
- return get_pin(SDA_MASK);
+ return get_pin(SDA_MASK, 3);
}
int get_scl(void)
{
- return get_pin(SCL_MASK);
+ return get_pin(SCL_MASK, 3);
}
-#if defined(CONFIG_HARD_I2C)
-static void setports(int gpio)
+int ft_board_setup(void *blob, bd_t *bd)
{
- ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
-
- if (gpio) {
- clrbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
- clrbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
- } else {
- setbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
- clrbits_be32(&iop->pdir, (SDA_MASK | SCL_MASK));
- setbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
- }
+ ft_cpu_setup(blob, bd);
+
+ return 0;
}
-#endif
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-void ft_board_setup(void *blob, bd_t *bd)
+
+#if defined(CONFIG_MGCOGE3NE)
+int get_testpin(void)
{
- ft_cpu_setup(blob, bd);
+ /* Testpin is Port C pin 29 - enable = low */
+ int testpin = !get_pin(0x00000004, 2);
+ return testpin;
}
-#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
+#endif
projects / platform / kernel / u-boot.git / blobdiff