Merge branch 'master' of git://git.denx.de/u-boot-arm

[platform/kernel/u-boot.git] / board / isee / igep0033 / board.c

diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
index ea3bea5..9f8fcf2 100644 (file)
--- a/board/isee/igep0033/board.c
+++ b/board/isee/igep0033/board.c
@@ -1,17 +1,9 @@
 /*
- * Board functions for IGEP COM AQUILA/CYGNUS based boards
+ * Board functions for IGEP COM AQUILA based boards
  *
  * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- * GNU General Public License for more details.
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -35,11 +27,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-
-/* MII mode defines */
-#define RMII_MODE_ENABLE       0x4D
-
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 
 #ifdef CONFIG_SPL_BUILD
@@ -48,20 +35,16 @@ static const struct ddr_data ddr3_data = {
        .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
        .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
        .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
-       .datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
 static const struct cmd_control ddr3_cmd_ctrl_data = {
        .cmd0csratio = K4B2G1646EBIH9_RATIO,
-       .cmd0dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
        .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
 
        .cmd1csratio = K4B2G1646EBIH9_RATIO,
-       .cmd1dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
        .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
 
        .cmd2csratio = K4B2G1646EBIH9_RATIO,
-       .cmd2dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
        .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
 };
 
@@ -74,60 +57,47 @@ static struct emif_regs ddr3_emif_reg_data = {
        .zq_config = K4B2G1646EBIH9_ZQ_CFG,
        .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
 };
-#endif
 
-/*
- * Early system init of muxing and clocks.
- */
-void s_init(void)
-{
-       /*
-        * Save the boot parameters passed from romcode.
-        * We cannot delay the saving further than this,
-        * to prevent overwrites.
-        */
-#ifdef CONFIG_SPL_BUILD
-       save_omap_boot_params();
-#endif
-
-       /* WDT1 is already running when the bootloader gets control
-        * Disable it to avoid "random" resets
-        */
-       writel(0xAAAA, &wdtimer->wdtwspr);
-       while (readl(&wdtimer->wdtwwps) != 0x0)
-               ;
-       writel(0x5555, &wdtimer->wdtwspr);
-       while (readl(&wdtimer->wdtwwps) != 0x0)
-               ;
+#define OSC    (V_OSCK/1000000)
+const struct dpll_params dpll_ddr = {
+               400, OSC-1, 1, -1, -1, -1, -1};
 
-#ifdef CONFIG_SPL_BUILD
-       /* Setup the PLLs and the clocks for the peripherals */
-       pll_init();
-
-       /* Enable RTC32K clock */
-       rtc32k_enable();
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+       return &dpll_ddr;
+}
 
+void set_uart_mux_conf(void)
+{
        enable_uart0_pin_mux();
+}
 
-       uart_soft_reset();
-       gd = &gdata;
-
-       preloader_console_init();
-
-       /* Configure board pin mux */
+void set_mux_conf_regs(void)
+{
        enable_board_pin_mux();
+}
 
-       config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
+const struct ctrl_ioregs ioregs = {
+       .cm0ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
+       .cm1ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
+       .cm2ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
+       .dt0ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
+       .dt1ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
+};
+
+void sdram_init(void)
+{
+       config_ddr(400, &ioregs, &ddr3_data,
                   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-#endif
 }
+#endif
 
 /*
  * Basic board specific setup.  Pinmux has been handled already.
  */
 int board_init(void)
 {
-       gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+       gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
        gpmc_init();
 
@@ -146,7 +116,7 @@ static struct cpsw_slave_data cpsw_slaves[] = {
        {
                .slave_reg_ofs  = 0x208,
                .sliver_reg_ofs = 0xd80,
-               .phy_id         = 0,
+               .phy_addr       = 0,
                .phy_if         = PHY_INTERFACE_MODE_RMII,
        },
 };
@@ -163,6 +133,7 @@ static struct cpsw_platform_data cpsw_data = {
        .ale_entries            = 1024,
        .host_port_reg_ofs      = 0x108,
        .hw_stats_reg_ofs       = 0x900,
+       .bd_ram_ofs             = 0x2000,
        .mac_control            = (1 << 5),
        .control                = cpsw_control,
        .host_port_num          = 0,
@@ -189,7 +160,8 @@ int board_eth_init(bd_t *bis)
                        eth_setenv_enetaddr("ethaddr", mac_addr);
        }
 
-       writel(RMII_MODE_ENABLE, &cdev->miisel);
+       writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
+              &cdev->miisel);
 
        rv = cpsw_register(&cpsw_data);
        if (rv < 0)
@@ -200,4 +172,3 @@ int board_eth_init(bd_t *bis)
        return ret;
 }
 #endif
-