* (C) Copyright 2009
* Grzegorz Bernacki, Semihalf, gjb@semihalf.com
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <i2c.h>
+#include <mb862xx.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_DIGSY_REV5)
/*
- * The M29W128GH needs a specail reset command function,
+ * The M29W128GH needs a special reset command function,
* details see the doc/README.cfi file
*/
void flash_cmd_reset(flash_info_t *info)
#endif
/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
* use of CONFIG_SYS_SDRAM_BASE. The code does not work if
- * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
+ * CONFIG_SYS_SDRAM_BASE is something other than 0x00000000.
*/
-phys_size_t initdram(int board_type)
+int dram_init(void)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
- return dramsize + dramsize2;
+ gd->ram_size = dramsize + dramsize2;
+
+ return 0;
}
int checkboard(void)
#define GPT_GPIO_ON 0x00000034 /* GPT as simple GPIO, high */
-/* ExBo I2C Addresses */
-#define EXBO_EE_I2C_ADDRESS 0x56
-
static void exbo_hw_init(void)
{
struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
struct mpc5xxx_wu_gpio *wu_gpio =
(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
- unsigned char val;
-
- /* 1st, check if extension board is present */
- if (i2c_read(EXBO_EE_I2C_ADDRESS, 0, 1, &val, 1))
- return;
/* configure IrDA pins (PSC6 port) as gpios */
gpio->port_config &= 0xFF8FFFFF;
int board_early_init_r(void)
{
-#ifdef CONFIG_MPC52XX_SPI
- struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt*)MPC5XXX_GPT;
-#endif
/*
* Now, when we are in RAM, enable flash write access for detection
* process. Note that CS_BOOT cannot be cleared when executing in
/* enable CS0 */
setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
- exbo_hw_init();
-
#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
/* Low level USB init, required for proper kernel operation */
usb_cpu_init();
#endif
-#ifdef CONFIG_MPC52XX_SPI
- /* GPT 6 Output Enable */
- out_be32(&gpt[6].emsr, 0x00000034);
- /* GPT 7 Output Enable */
- out_be32(&gpt[7].emsr, 0x00000034);
-#endif
return (0);
}
int misc_init_r(void)
{
+ pci_dev_t devbusfn;
uchar enetaddr[6];
+ /* check if graphic extension board is present */
+ devbusfn = pci_find_device(PCI_VENDOR_ID_FUJITSU,
+ PCI_DEVICE_ID_CORAL_PA, 0);
+ if (devbusfn != -1)
+ exbo_hw_init();
+
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
board_get_enetaddr(enetaddr);
eth_setenv_enetaddr("ethaddr", enetaddr);
}
#endif
-#ifdef CONFIG_CMD_IDE
+#ifdef CONFIG_IDE
#ifdef CONFIG_IDE_RESET
setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
}
#endif /* CONFIG_IDE_RESET */
-#endif /* CONFIG_CMD_IDE */
+#endif /* CONFIG_IDE */
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
static void ft_delete_node(void *fdt, const char *compat)
{
int off = -1;
}
#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
int phy_addr = CONFIG_PHY_ADDR;
char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
#endif
/* fix up the phy address */
do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
+
+ return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */