odroid: remove CONFIG_DM_I2C_COMPAT config

[platform/kernel/u-boot.git] / board / intercontrol / digsy_mtc / digsy_mtc.c

diff --git a/board/intercontrol/digsy_mtc/digsy_mtc.c b/board/intercontrol/digsy_mtc/digsy_mtc.c
index 2e52d51..6c33eeb 100644 (file)
--- a/board/intercontrol/digsy_mtc/digsy_mtc.c
+++ b/board/intercontrol/digsy_mtc/digsy_mtc.c
@@ -41,7 +41,7 @@ extern int usb_cpu_init(void);
 
 #if defined(CONFIG_DIGSY_REV5)
 /*
- * The M29W128GH needs a specail reset command function,
+ * The M29W128GH needs a special reset command function,
  * details see the doc/README.cfi file
  */
 void flash_cmd_reset(flash_info_t *info)
@@ -74,12 +74,12 @@ static void sdram_start(int hi_addr)
 #endif
 
 /*
- * ATTENTION: Although partially referenced initdram does NOT make real use
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
  *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if
- *            CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
+ *            CONFIG_SYS_SDRAM_BASE is something other than 0x00000000.
  */
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
        ulong dramsize = 0;
        ulong dramsize2 = 0;
@@ -172,7 +172,9 @@ phys_size_t initdram(int board_type)
            (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
                out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
 
-       return dramsize + dramsize2;
+       gd->ram_size = dramsize + dramsize2;
+
+       return 0;
 }
 
 int checkboard(void)
@@ -250,9 +252,6 @@ static inline void exbo_hw_init(void) {}
 
 int board_early_init_r(void)
 {
-#ifdef CONFIG_MPC52XX_SPI
-       struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt*)MPC5XXX_GPT;
-#endif
        /*
         * Now, when we are in RAM, enable flash write access for detection
         * process.  Note that CS_BOOT cannot be cleared when executing in
@@ -269,12 +268,6 @@ int board_early_init_r(void)
        /* Low level USB init, required for proper kernel operation */
        usb_cpu_init();
 #endif
-#ifdef CONFIG_MPC52XX_SPI
-       /* GPT 6 Output Enable */
-       out_be32(&gpt[6].emsr, 0x00000034);
-       /* GPT 7 Output Enable */
-       out_be32(&gpt[7].emsr, 0x00000034);
-#endif
 
        return (0);
 }
@@ -332,7 +325,7 @@ void pci_init_board(void)
 }
 #endif
 
-#ifdef CONFIG_CMD_IDE
+#ifdef CONFIG_IDE
 
 #ifdef CONFIG_IDE_RESET
 
@@ -376,7 +369,7 @@ void ide_set_reset(int idereset)
        setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
 }
 #endif /* CONFIG_IDE_RESET */
-#endif /* CONFIG_CMD_IDE */
+#endif /* CONFIG_IDE */
 
 #ifdef CONFIG_OF_BOARD_SETUP
 static void ft_delete_node(void *fdt, const char *compat)