ppc4xx: Big cleanup of PPC4xx defines

[platform/kernel/u-boot.git] / board / gdsys / gdppc440etx / gdppc440etx.c

diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c
index a661057..27c159b 100644 (file)
--- a/board/gdsys/gdppc440etx/gdppc440etx.c
+++ b/board/gdsys/gdppc440etx/gdppc440etx.c
@@ -42,8 +42,8 @@ int board_early_init_f(void)
        /*
         * Setup the external bus controller/chip selects
         */
-       mfebc(xbcfg, reg);
-       mtebc(xbcfg, reg | 0x04000000);         /* Set ATC */
+       mfebc(EBC0_CFG, reg);
+       mtebc(EBC0_CFG, reg | 0x04000000);              /* Set ATC */
 
        /*
         * Setup the GPIO pins
@@ -102,10 +102,10 @@ int board_early_init_f(void)
        /*
         * Setup other serial configuration
         */
-       mfsdr(sdr_pci0, reg);
-       mtsdr(sdr_pci0, 0x80000000 | reg);      /* PCI arbiter enabled */
-       mtsdr(sdr_pfc0, 0x00003e00);    /* Pin function */
-       mtsdr(sdr_pfc1, 0x00048000);    /* Pin function: UART0 has 4 pins */
+       mfsdr(SDR0_PCI0, reg);
+       mtsdr(SDR0_PCI0, 0x80000000 | reg);     /* PCI arbiter enabled */
+       mtsdr(SDR0_PFC0, 0x00003e00);   /* Pin function */
+       mtsdr(SDR0_PFC1, 0x00048000);   /* Pin function: UART0 has 4 pins */
 
        return 0;
 }
@@ -117,7 +117,7 @@ int misc_init_r(void)
        uint sz;
 
        /* Re-do sizing to get full correct info */
-       mfebc(pb0cr, pbcr);
+       mfebc(PB0CR, pbcr);
 
        if (gd->bd->bi_flashsize > 0x08000000)
                panic("Max. flash banksize is 128 MB!\n");
@@ -127,7 +127,7 @@ int misc_init_r(void)
                sz <<= 1;
 
        pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
-       mtebc(pb0cr, pbcr);
+       mtebc(PB0CR, pbcr);
 
        /* adjust flash start and offset */
        gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
@@ -178,35 +178,35 @@ int pci_pre_init(struct pci_controller *hose)
         * Set priority for all PLB3 devices to 0.
         * Set PLB3 arbiter to fair mode.
         */
-       mfsdr(sdr_amp1, addr);
-       mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
-       addr = mfdcr(plb3_acr);
-       mtdcr(plb3_acr, addr | 0x80000000);
+       mfsdr(SD0_AMP1, addr);
+       mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
+       addr = mfdcr(PLB3_ACR);
+       mtdcr(PLB3_ACR, addr | 0x80000000);
 
        /*
         * Set priority for all PLB4 devices to 0.
         */
-       mfsdr(sdr_amp0, addr);
-       mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
-       addr = mfdcr(plb4_acr) | 0xa0000000;    /* Was 0x8---- */
-       mtdcr(plb4_acr, addr);
+       mfsdr(SD0_AMP0, addr);
+       mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
+       addr = mfdcr(PLB4_ACR) | 0xa0000000;    /* Was 0x8---- */
+       mtdcr(PLB4_ACR, addr);
 
        /*
         * Set Nebula PLB4 arbiter to fair mode.
         */
        /* Segment0 */
-       addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
-       addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
-       addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
-       addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
-       mtdcr(plb0_acr, addr);
+       addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
+       addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
+       addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
+       addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
+       mtdcr(PLB0_ACR, addr);
 
        /* Segment1 */
-       addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
-       addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
-       addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
-       addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
-       mtdcr(plb1_acr, addr);
+       addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
+       addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
+       addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
+       addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
+       mtdcr(PLB1_ACR, addr);
 
        /* enable 66 MHz ext. Clock */
        out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000);