drivers, block: remove sil680 driver

[platform/kernel/u-boot.git] / board / gdsys / 405ep / io.c

diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c
index 070dcbb..1484469 100644 (file)
--- a/board/gdsys/405ep/io.c
+++ b/board/gdsys/405ep/io.c
@@ -2,23 +2,7 @@
  * (C) Copyright 2010
  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -27,7 +11,6 @@
 #include <asm/io.h>
 #include <asm/ppc4xx-gpio.h>
 
-#include <dtt.h>
 #include <miiphy.h>
 
 #include "405ep.h"
@@ -53,10 +36,17 @@ enum {
        HWVER_122 = 3,
 };
 
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
 int misc_init_r(void)
 {
-       /* startup fans */
-       dtt_init();
+       /*
+        * Note: DTT has been removed. Please use UCLASS_THERMAL.
+        *
+        * startup fans
+        *
+        * dtt_init();
+        */
 
        return 0;
 }
@@ -117,15 +107,18 @@ int checkboard(void)
 
 static void print_fpga_info(void)
 {
-       struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
-       u16 versions = in_le16(&fpga->versions);
-       u16 fpga_version = in_le16(&fpga->fpga_version);
-       u16 fpga_features = in_le16(&fpga->fpga_features);
+       u16 versions;
+       u16 fpga_version;
+       u16 fpga_features;
        unsigned unit_type;
        unsigned hardware_version;
        unsigned feature_channels;
        unsigned feature_expansion;
 
+       FPGA_GET_REG(0, versions, &versions);
+       FPGA_GET_REG(0, fpga_version, &fpga_version);
+       FPGA_GET_REG(0, fpga_features, &fpga_features);
+
        unit_type = (versions & 0xf000) >> 12;
        hardware_version = versions & 0x000f;
        feature_channels = fpga_features & 0x007f;
@@ -179,19 +172,27 @@ static void print_fpga_info(void)
  */
 int last_stage_init(void)
 {
-       struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
        unsigned int k;
 
        print_fpga_info();
 
-       miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
-               bb_miiphy_read, bb_miiphy_write);
+       int retval;
+       struct mii_dev *mdiodev = mdio_alloc();
+       if (!mdiodev)
+               return -ENOMEM;
+       strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII_BUSNAME, MDIO_NAME_LEN);
+       mdiodev->read = bb_miiphy_read;
+       mdiodev->write = bb_miiphy_write;
+
+       retval = mdio_register(mdiodev);
+       if (retval < 0)
+               return retval;
 
        for (k = 0; k < 32; ++k)
                configure_gbit_phy(k);
 
        /* take fpga serdes blocks out of reset */
-       out_le16(&fpga->quad_serdes_reset, 0);
+       FPGA_SET_REG(0, quad_serdes_reset, 0);
 
        return 0;
 }