*/
#include <common.h>
-#include <asm/io.h>
#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/mxc_hdmi.h>
-#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/sata.h>
+#include <asm/imx-common/spi.h>
#include <asm/imx-common/video.h>
-#include <jffs2/load_kernel.h>
-#include <hwconfig.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/platform_data/serial_mxc.h>
#include <i2c.h>
-#include <linux/ctype.h>
#include <fdt_support.h>
#include <fsl_esdhc.h>
+#include <jffs2/load_kernel.h>
+#include <linux/ctype.h>
#include <miiphy.h>
-#include <mmc.h>
#include <mtd_node.h>
#include <netdev.h>
+#include <pci.h>
#include <power/pmic.h>
#include <power/ltc3676_pmic.h>
#include <power/pfuze100_pmic.h>
#include <spi_flash.h>
#include "gsc.h"
-#include "ventana_eeprom.h"
+#include "common.h"
DECLARE_GLOBAL_DATA_PTR;
-/* GPIO's common to all baseboards */
-#define GP_PHY_RST IMX_GPIO_NR(1, 30)
-#define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
-#define GP_SD3_CD IMX_GPIO_NR(7, 0)
-#define GP_RS232_EN IMX_GPIO_NR(2, 11)
-#define GP_MSATA_SEL IMX_GPIO_NR(2, 8)
-
-/* I2C bus numbers */
-#define I2C_GSC 0
-#define I2C_PMIC 1
-
-#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define SPI_PAD_CTRL (PAD_CTL_HYS | \
- PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define DIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
-
-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE | PAD_CTL_SRE_FAST)
/*
* EEPROM board info struct populated by read_eeprom so that we only have to
* read it once.
*/
-static struct ventana_board_info ventana_info;
-
-enum {
- GW54proto, /* original GW5400-A prototype */
- GW51xx,
- GW52xx,
- GW53xx,
- GW54xx,
- GW_UNKNOWN,
-};
-
-int board_type;
-
-/* UART1: Function varies per baseboard */
-iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-/* UART2: Serial Console */
-iomux_v3_cfg_t const uart2_pads[] = {
- MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-/* I2C1: GSC */
-struct i2c_pads_info i2c_pad_info0 = {
- .scl = {
- .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
- .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
- .gp = IMX_GPIO_NR(3, 21)
- },
- .sda = {
- .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
- .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
- .gp = IMX_GPIO_NR(3, 28)
- }
-};
+struct ventana_board_info ventana_info;
-/* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
-struct i2c_pads_info i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
- .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
- .gp = IMX_GPIO_NR(4, 12)
- },
- .sda = {
- .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
-/* I2C3: Misc/Expansion */
-struct i2c_pads_info i2c_pad_info2 = {
- .scl = {
- .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
- .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
- .gp = IMX_GPIO_NR(1, 3)
- },
- .sda = {
- .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
- .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
- .gp = IMX_GPIO_NR(1, 6)
- }
-};
+static int board_type;
/* MMC */
-iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ /* CD */
+ IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
};
/* ENET */
-iomux_v3_cfg_t const enet_pads[] = {
- MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+static iomux_v3_cfg_t const enet_pads[] = {
+ IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
+ MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
+ MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
+ MUX_PAD_CTRL(ENET_PAD_CTRL)),
/* PHY nRST */
- MX6_PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
};
/* NAND */
-iomux_v3_cfg_t const nfc_pads[] = {
- MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+static iomux_v3_cfg_t const nfc_pads[] = {
+ IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
#ifdef CONFIG_CMD_NAND
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
/* config gpmi nand iomux */
- imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
+ SETUP_IOMUX_PADS(nfc_pads);
/* config gpmi and bch clock to 100 MHz */
clrsetbits_le32(&mxc_ccm->cs2cdr,
}
#endif
-static void setup_iomux_enet(void)
+static void setup_iomux_enet(int gpio)
{
- imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+ SETUP_IOMUX_PADS(enet_pads);
/* toggle PHY_RST# */
- gpio_direction_output(GP_PHY_RST, 0);
+ gpio_request(gpio, "phy_rst#");
+ gpio_direction_output(gpio, 0);
mdelay(2);
- gpio_set_value(GP_PHY_RST, 1);
-}
-
-static void setup_iomux_uart(void)
-{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
- imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+ gpio_set_value(gpio, 1);
}
#ifdef CONFIG_USB_EHCI_MX6
-iomux_v3_cfg_t const usb_pads[] = {
- MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(DIO_PAD_CTRL),
- MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(DIO_PAD_CTRL),
- MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(DIO_PAD_CTRL), /* OTG PWR */
+static iomux_v3_cfg_t const usb_pads[] = {
+ IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
+ IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
+ /* OTG PWR */
+ IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG),
};
int board_ehci_hcd_init(int port)
{
- struct ventana_board_info *info = &ventana_info;
+ int gpio;
- imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
+ SETUP_IOMUX_PADS(usb_pads);
- /* Reset USB HUB (present on GW54xx/GW53xx) */
- switch (info->model[3]) {
- case '3': /* GW53xx */
- imx_iomux_v3_setup_pad(MX6_PAD_GPIO_9__GPIO1_IO09|
- MUX_PAD_CTRL(NO_PAD_CTRL));
- gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
- mdelay(2);
- gpio_set_value(IMX_GPIO_NR(1, 9), 1);
+ /* Reset USB HUB */
+ switch (board_type) {
+ case GW53xx:
+ case GW552x:
+ gpio = (IMX_GPIO_NR(1, 9));
break;
- case '4': /* GW54xx */
- imx_iomux_v3_setup_pad(MX6_PAD_SD1_DAT0__GPIO1_IO16 |
- MUX_PAD_CTRL(NO_PAD_CTRL));
- gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
- mdelay(2);
- gpio_set_value(IMX_GPIO_NR(1, 16), 1);
+ case GW54proto:
+ case GW54xx:
+ gpio = (IMX_GPIO_NR(1, 16));
break;
+ default:
+ return 0;
}
+ /* request and toggle hub rst */
+ gpio_request(gpio, "usb_hub_rst#");
+ gpio_direction_output(gpio, 0);
+ mdelay(2);
+ gpio_set_value(gpio, 1);
+
return 0;
}
#endif /* CONFIG_USB_EHCI_MX6 */
#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
+static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
int board_mmc_getcd(struct mmc *mmc)
{
/* Card Detect */
+ gpio_request(GP_SD3_CD, "sd_cd");
gpio_direction_input(GP_SD3_CD);
return !gpio_get_value(GP_SD3_CD);
}
int board_mmc_init(bd_t *bis)
{
/* Only one USDHC controller on Ventana */
- imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ SETUP_IOMUX_PADS(usdhc3_pads);
usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg.max_bus_width = 4;
#ifdef CONFIG_MXC_SPI
iomux_v3_cfg_t const ecspi1_pads[] = {
/* SS1 */
- MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
};
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
+}
+
static void setup_spi(void)
{
- gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
- imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
- ARRAY_SIZE(ecspi1_pads));
+ gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
+ gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
+ SETUP_IOMUX_PADS(ecspi1_pads);
}
#endif
int board_eth_init(bd_t *bis)
{
- setup_iomux_enet();
-
#ifdef CONFIG_FEC_MXC
- cpu_eth_init(bis);
+ if (board_type != GW551x && board_type != GW552x) {
+ setup_iomux_enet(GP_PHY_RST);
+ cpu_eth_init(bis);
+ }
+#endif
+
+#ifdef CONFIG_E1000
+ e1000_initialize(bis);
#endif
#ifdef CONFIG_CI_UDC
usb_eth_initialize(bis);
#endif
+ /* default to the first detected enet dev */
+ if (!getenv("ethprime")) {
+ struct eth_device *dev = eth_get_dev_by_index(0);
+ if (dev) {
+ setenv("ethprime", dev->name);
+ printf("set ethprime to %s\n", getenv("ethprime"));
+ }
+ }
+
return 0;
}
writel(reg, &iomux->gpr[2]);
/* Enable Backlight */
- imx_iomux_v3_setup_pad(MX6_PAD_SD1_CMD__GPIO1_IO18 |
- MUX_PAD_CTRL(NO_PAD_CTRL));
+ gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
+ SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
}
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
+} }, {
+ /* DLC700JMG-T-4 */
+ .bus = 0,
+ .addr = 0,
+ .detect = NULL,
+ .enable = enable_lvds,
+ .pixfmt = IPU_PIX_FMT_LVDS666,
+ .mode = {
+ .name = "DLC700JMGT4",
+ .refresh = 60,
+ .xres = 1024, /* 1024x600active pixels */
+ .yres = 600,
+ .pixclock = 15385, /* 64MHz */
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ /* DLC800FIG-T-3 */
+ .bus = 0,
+ .addr = 0,
+ .detect = NULL,
+ .enable = enable_lvds,
+ .pixfmt = IPU_PIX_FMT_LVDS666,
+ .mode = {
+ .name = "DLC800FIGT3",
+ .refresh = 60,
+ .xres = 1024, /* 1024x768 active pixels */
+ .yres = 768,
+ .pixclock = 15385, /* 64MHz */
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
} } };
size_t display_count = ARRAY_SIZE(displays);
writel(reg, &iomux->gpr[3]);
/* Backlight CABEN on LVDS connector */
- imx_iomux_v3_setup_pad(MX6_PAD_SD2_CLK__GPIO1_IO10 |
- MUX_PAD_CTRL(NO_PAD_CTRL));
+ gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
+ SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
}
#endif /* CONFIG_VIDEO_IPUV3 */
-/* read ventana EEPROM, check for validity, and return baseboard type */
-static int
-read_eeprom(void)
-{
- int i;
- int chksum;
- char baseboard;
- int type;
- struct ventana_board_info *info = &ventana_info;
- unsigned char *buf = (unsigned char *)&ventana_info;
-
- memset(info, 0, sizeof(ventana_info));
-
- /*
- * On a board with a missing/depleted backup battery for GSC, the
- * board may be ready to probe the GSC before its firmware is
- * running. We will wait here indefinately for the GSC/EEPROM.
- */
- while (1) {
- if (0 == i2c_set_bus_num(I2C_GSC) &&
- 0 == i2c_probe(GSC_EEPROM_ADDR))
- break;
- mdelay(1);
- }
-
- /* read eeprom config section */
- if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(ventana_info))) {
- puts("EEPROM: Failed to read EEPROM\n");
- info->model[0] = 0;
- return GW_UNKNOWN;
- }
-
- /* sanity checks */
- if (info->model[0] != 'G' || info->model[1] != 'W') {
- puts("EEPROM: Invalid Model in EEPROM\n");
- info->model[0] = 0;
- return GW_UNKNOWN;
- }
-
- /* validate checksum */
- for (chksum = 0, i = 0; i < sizeof(*info)-2; i++)
- chksum += buf[i];
- if ((info->chksum[0] != chksum>>8) ||
- (info->chksum[1] != (chksum&0xff))) {
- puts("EEPROM: Failed EEPROM checksum\n");
- info->model[0] = 0;
- return GW_UNKNOWN;
- }
-
- /* original GW5400-A prototype */
- baseboard = info->model[3];
- if (strncasecmp((const char *)info->model, "GW5400-A", 8) == 0)
- baseboard = '0';
-
- switch (baseboard) {
- case '0': /* original GW5400-A prototype */
- type = GW54proto;
- break;
- case '1':
- type = GW51xx;
- break;
- case '2':
- type = GW52xx;
- break;
- case '3':
- type = GW53xx;
- break;
- case '4':
- type = GW54xx;
- break;
- default:
- printf("EEPROM: Unknown model in EEPROM: %s\n", info->model);
- type = GW_UNKNOWN;
- break;
- }
- return type;
-}
-
-/*
- * Baseboard specific GPIO
- */
-
-/* common to add baseboards */
-static iomux_v3_cfg_t const gw_gpio_pads[] = {
- /* MSATA_EN */
- MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* RS232_EN# */
- MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-/* prototype */
-static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
- /* PANLEDG# */
- MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* PANLEDR# */
- MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* LOCLED# */
- MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* RS485_EN */
- MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* IOEXP_PWREN# */
- MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* IOEXP_IRQ# */
- MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* VID_EN */
- MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* DIOI2C_DIS# */
- MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* PCICK_SSON */
- MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* PCI_RST# */
- MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
- /* PANLEDG# */
- MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* PANLEDR# */
- MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* IOEXP_PWREN# */
- MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* IOEXP_IRQ# */
- MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
-
- /* GPS_SHDN */
- MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* VID_PWR */
- MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* PCI_RST# */
- MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
- /* PANLEDG# */
- MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* PANLEDR# */
- MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* IOEXP_PWREN# */
- MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* IOEXP_IRQ# */
- MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
-
- /* MX6_LOCLED# */
- MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* GPS_SHDN */
- MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* USBOTG_SEL */
- MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* VID_PWR */
- MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* PCI_RST# */
- MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
- /* PANLEDG# */
- MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* PANLEDR# */
- MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* IOEXP_PWREN# */
- MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* IOEXP_IRQ# */
- MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
-
- /* MX6_LOCLED# */
- MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* GPS_SHDN */
- MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* VID_EN */
- MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* PCI_RST# */
- MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
- /* PANLEDG# */
- MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* PANLEDR# */
- MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* MX6_LOCLED# */
- MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* MIPI_DIO */
- MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* RS485_EN */
- MX6_PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* IOEXP_PWREN# */
- MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* IOEXP_IRQ# */
- MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* DIOI2C_DIS# */
- MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* DIOI2C_DIS# */
- MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* PCICK_SSON */
- MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* PCI_RST# */
- MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-/*
- * each baseboard has 4 user configurable Digital IO lines which can
- * be pinmuxed as a GPIO or in some cases a PWM
- */
-struct dio_cfg {
- iomux_v3_cfg_t gpio_padmux;
- unsigned gpio_param;
- iomux_v3_cfg_t pwm_padmux;
- unsigned pwm_param;
-};
-
-struct ventana {
- /* pinmux */
- iomux_v3_cfg_t const *gpio_pads;
- int num_pads;
- /* DIO pinmux/val */
- struct dio_cfg dio_cfg[4];
- /* various gpios (0 if non-existent) */
- int leds[3];
- int pcie_rst;
- int mezz_pwren;
- int mezz_irq;
- int rs485en;
- int gps_shdn;
- int vidin_en;
- int dioi2c_en;
- int pcie_sson;
- int usb_sel;
-};
-
-struct ventana gpio_cfg[] = {
- /* GW5400proto */
- {
- .gpio_pads = gw54xx_gpio_pads,
- .num_pads = ARRAY_SIZE(gw54xx_gpio_pads),
- .dio_cfg = {
- { MX6_PAD_GPIO_9__GPIO1_IO09, IMX_GPIO_NR(1, 9),
- MX6_PAD_GPIO_9__PWM1_OUT, 1 },
- { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
- MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
- { MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9),
- MX6_PAD_SD4_DAT1__PWM3_OUT, 3 },
- { MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10),
- MX6_PAD_SD4_DAT2__PWM4_OUT, 4 },
- },
- .leds = {
- IMX_GPIO_NR(4, 6),
- IMX_GPIO_NR(4, 10),
- IMX_GPIO_NR(4, 15),
- },
- .pcie_rst = IMX_GPIO_NR(1, 29),
- .mezz_pwren = IMX_GPIO_NR(4, 7),
- .mezz_irq = IMX_GPIO_NR(4, 9),
- .rs485en = IMX_GPIO_NR(3, 24),
- .dioi2c_en = IMX_GPIO_NR(4, 5),
- .pcie_sson = IMX_GPIO_NR(1, 20),
- },
-
- /* GW51xx */
- {
- .gpio_pads = gw51xx_gpio_pads,
- .num_pads = ARRAY_SIZE(gw51xx_gpio_pads),
- .dio_cfg = {
- { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
- 0, 0 },
- { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
- MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
- { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
- MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
- { MX6_PAD_SD1_CMD__GPIO1_IO18, IMX_GPIO_NR(1, 18),
- MX6_PAD_SD1_CMD__PWM4_OUT, 4 },
- },
- .leds = {
- IMX_GPIO_NR(4, 6),
- IMX_GPIO_NR(4, 10),
- },
- .pcie_rst = IMX_GPIO_NR(1, 0),
- .mezz_pwren = IMX_GPIO_NR(2, 19),
- .mezz_irq = IMX_GPIO_NR(2, 18),
- .gps_shdn = IMX_GPIO_NR(1, 2),
- .vidin_en = IMX_GPIO_NR(5, 20),
- },
-
- /* GW52xx */
- {
- .gpio_pads = gw52xx_gpio_pads,
- .num_pads = ARRAY_SIZE(gw52xx_gpio_pads),
- .dio_cfg = {
- { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
- 0, 0 },
- { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
- MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
- { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
- MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
- { MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20),
- 0, 0 },
- },
- .leds = {
- IMX_GPIO_NR(4, 6),
- IMX_GPIO_NR(4, 7),
- IMX_GPIO_NR(4, 15),
- },
- .pcie_rst = IMX_GPIO_NR(1, 29),
- .mezz_pwren = IMX_GPIO_NR(2, 19),
- .mezz_irq = IMX_GPIO_NR(2, 18),
- .gps_shdn = IMX_GPIO_NR(1, 27),
- .vidin_en = IMX_GPIO_NR(3, 31),
- .usb_sel = IMX_GPIO_NR(1, 2),
- },
-
- /* GW53xx */
- {
- .gpio_pads = gw53xx_gpio_pads,
- .num_pads = ARRAY_SIZE(gw53xx_gpio_pads),
- .dio_cfg = {
- { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
- 0, 0 },
- { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
- MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
- { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
- MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
- { MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20),
- 0, 0 },
- },
- .leds = {
- IMX_GPIO_NR(4, 6),
- IMX_GPIO_NR(4, 7),
- IMX_GPIO_NR(4, 15),
- },
- .pcie_rst = IMX_GPIO_NR(1, 29),
- .mezz_pwren = IMX_GPIO_NR(2, 19),
- .mezz_irq = IMX_GPIO_NR(2, 18),
- .gps_shdn = IMX_GPIO_NR(1, 27),
- .vidin_en = IMX_GPIO_NR(3, 31),
- },
-
- /* GW54xx */
- {
- .gpio_pads = gw54xx_gpio_pads,
- .num_pads = ARRAY_SIZE(gw54xx_gpio_pads),
- .dio_cfg = {
- { MX6_PAD_GPIO_9__GPIO1_IO09, IMX_GPIO_NR(1, 9),
- MX6_PAD_GPIO_9__PWM1_OUT, 1 },
- { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
- MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
- { MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9),
- MX6_PAD_SD4_DAT1__PWM3_OUT, 3 },
- { MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10),
- MX6_PAD_SD4_DAT2__PWM4_OUT, 4 },
- },
- .leds = {
- IMX_GPIO_NR(4, 6),
- IMX_GPIO_NR(4, 7),
- IMX_GPIO_NR(4, 15),
- },
- .pcie_rst = IMX_GPIO_NR(1, 29),
- .mezz_pwren = IMX_GPIO_NR(2, 19),
- .mezz_irq = IMX_GPIO_NR(2, 18),
- .rs485en = IMX_GPIO_NR(7, 1),
- .vidin_en = IMX_GPIO_NR(3, 31),
- .dioi2c_en = IMX_GPIO_NR(4, 5),
- .pcie_sson = IMX_GPIO_NR(1, 20),
- },
-};
-
/* setup board specific PMIC */
int power_init_board(void)
{
- struct pmic *p;
- u32 reg;
-
- /* configure PFUZE100 PMIC */
- if (board_type == GW54xx || board_type == GW54proto) {
- power_pfuze100_init(I2C_PMIC);
- p = pmic_get("PFUZE100_PMIC");
- if (p && !pmic_probe(p)) {
- pmic_reg_read(p, PFUZE100_DEVICEID, ®);
- printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
-
- /* Set VGEN1 to 1.5V and enable */
- pmic_reg_read(p, PFUZE100_VGEN1VOL, ®);
- reg &= ~(LDO_VOL_MASK);
- reg |= (LDOA_1_50V | LDO_EN);
- pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
-
- /* Set SWBST to 5.0V and enable */
- pmic_reg_read(p, PFUZE100_SWBSTCON1, ®);
- reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
- reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
- pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
- }
- }
-
- /* configure LTC3676 PMIC */
- else {
- power_ltc3676_init(I2C_PMIC);
- p = pmic_get("LTC3676_PMIC");
- if (p && !pmic_probe(p)) {
- puts("PMIC: LTC3676\n");
- /* set board-specific scalar to 1225mV for IMX6Q@1GHz */
- if (is_cpu_type(MXC_CPU_MX6Q)) {
- /* mask PGOOD during SW1 transition */
- reg = 0x1d | LTC3676_PGOOD_MASK;
- pmic_reg_write(p, LTC3676_DVB1B, reg);
- /* set SW1 (VDD_SOC) to 1259mV */
- reg = 0x1d;
- pmic_reg_write(p, LTC3676_DVB1A, reg);
-
- /* mask PGOOD during SW3 transition */
- reg = 0x1d | LTC3676_PGOOD_MASK;
- pmic_reg_write(p, LTC3676_DVB3B, reg);
- /*set SW3 (VDD_ARM) to 1259mV */
- reg = 0x1d;
- pmic_reg_write(p, LTC3676_DVB3A, reg);
- }
- }
- }
-
+ setup_pmic();
return 0;
}
-/* setup GPIO pinmux and default configuration per baseboard */
-static void setup_board_gpio(int board)
-{
- struct ventana_board_info *info = &ventana_info;
- const char *s;
- char arg[10];
- size_t len;
- int i;
- int quiet = simple_strtol(getenv("quiet"), NULL, 10);
-
- if (board >= GW_UNKNOWN)
- return;
-
- /* RS232_EN# */
- gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
-
- /* MSATA Enable */
- if (is_cpu_type(MXC_CPU_MX6Q) &&
- test_bit(EECONFIG_SATA, info->config)) {
- gpio_direction_output(GP_MSATA_SEL,
- (hwconfig("msata")) ? 1 : 0);
- } else {
- gpio_direction_output(GP_MSATA_SEL, 0);
- }
-
- /*
- * assert PCI_RST# (released by OS when clock is valid)
- * TODO: figure out why leaving this de-asserted from PCI scan on boot
- * causes linux pcie driver to hang during enumeration
- */
- gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
-
- /* turn off (active-high) user LED's */
- for (i = 0; i < 4; i++) {
- if (gpio_cfg[board].leds[i])
- gpio_direction_output(gpio_cfg[board].leds[i], 1);
- }
-
- /* Expansion Mezzanine IO */
- gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
- gpio_direction_input(gpio_cfg[board].mezz_irq);
-
- /* RS485 Transmit Enable */
- if (gpio_cfg[board].rs485en)
- gpio_direction_output(gpio_cfg[board].rs485en, 0);
-
- /* GPS_SHDN */
- if (gpio_cfg[board].gps_shdn)
- gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
-
- /* Analog video codec power enable */
- if (gpio_cfg[board].vidin_en)
- gpio_direction_output(gpio_cfg[board].vidin_en, 1);
-
- /* DIOI2C_DIS# */
- if (gpio_cfg[board].dioi2c_en)
- gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
-
- /* PCICK_SSON: disable spread-spectrum clock */
- if (gpio_cfg[board].pcie_sson)
- gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
-
- /* USBOTG Select (PCISKT or FrontPanel) */
- if (gpio_cfg[board].usb_sel)
- gpio_direction_output(gpio_cfg[board].usb_sel, 0);
-
- /*
- * Configure DIO pinmux/padctl registers
- * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
- */
- for (i = 0; i < 4; i++) {
- struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
- unsigned ctrl = DIO_PAD_CTRL;
-
- sprintf(arg, "dio%d", i);
- if (!hwconfig(arg))
- continue;
- s = hwconfig_subarg(arg, "padctrl", &len);
- if (s)
- ctrl = simple_strtoul(s, NULL, 16) & 0x3ffff;
- if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
- if (!quiet) {
- printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i,
- (cfg->gpio_param/32)+1,
- cfg->gpio_param%32,
- cfg->gpio_param);
- }
- imx_iomux_v3_setup_pad(cfg->gpio_padmux |
- MUX_PAD_CTRL(ctrl));
- gpio_direction_input(cfg->gpio_param);
- } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
- cfg->pwm_padmux) {
- if (!quiet)
- printf("DIO%d: pwm%d\n", i, cfg->pwm_param);
- imx_iomux_v3_setup_pad(cfg->pwm_padmux |
- MUX_PAD_CTRL(ctrl));
- }
- }
-
- if (!quiet) {
- if (is_cpu_type(MXC_CPU_MX6Q) &&
- (test_bit(EECONFIG_SATA, info->config))) {
- printf("MSATA: %s\n", (hwconfig("msata") ?
- "enabled" : "disabled"));
- }
- printf("RS232: %s\n", (hwconfig("rs232")) ?
- "enabled" : "disabled");
- }
-}
-
#if defined(CONFIG_CMD_PCI)
int imx6_pcie_toggle_reset(void)
{
if (board_type < GW_UNKNOWN) {
- gpio_direction_output(gpio_cfg[board_type].pcie_rst, 0);
+ uint pin = gpio_cfg[board_type].pcie_rst;
+ gpio_request(pin, "pci_rst#");
+ gpio_direction_output(pin, 0);
mdelay(50);
- gpio_direction_output(gpio_cfg[board_type].pcie_rst, 1);
+ gpio_direction_output(pin, 1);
}
return 0;
}
+
+/*
+ * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
+ * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
+ * properly and assert reset for 100ms.
+ */
+void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
+ unsigned short vendor, unsigned short device,
+ unsigned short class)
+{
+ u32 dw;
+
+ debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
+ PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
+ if (vendor == PCI_VENDOR_ID_PLX &&
+ (device & 0xfff0) == 0x8600 &&
+ PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
+ debug("configuring PLX 860X downstream PERST#\n");
+ pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
+ dw |= 0xaaa8; /* GPIO1-7 outputs */
+ pci_hose_write_config_dword(hose, dev, 0x62c, dw);
+
+ pci_hose_read_config_dword(hose, dev, 0x644, &dw);
+ dw |= 0xfe; /* GPIO1-7 output high */
+ pci_hose_write_config_dword(hose, dev, 0x644, dw);
+
+ mdelay(100);
+ }
+}
#endif /* CONFIG_CMD_PCI */
#ifdef CONFIG_SERIAL_TAG
int board_early_init_f(void)
{
setup_iomux_uart();
- gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
#if defined(CONFIG_VIDEO_IPUV3)
setup_display();
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
- CONFIG_DDR_MB*1024*1024);
-
+ gd->ram_size = imx_ddr_size();
return 0;
}
int board_init(void)
{
- struct iomuxc_base_regs *const iomuxc_regs
- = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
clrsetbits_le32(&iomuxc_regs->gpr[1],
IOMUXC_GPR1_OTG_ID_MASK,
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+ setup_ventana_i2c();
#ifdef CONFIG_CMD_SATA
setup_sata();
#endif
/* read Gateworks EEPROM into global struct (used later) */
- board_type = read_eeprom();
+ board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
- /* board-specifc GPIO iomux */
- if (board_type < GW_UNKNOWN) {
- imx_iomux_v3_setup_multiple_pads(gw_gpio_pads,
- ARRAY_SIZE(gw_gpio_pads));
- imx_iomux_v3_setup_multiple_pads(gpio_cfg[board_type].gpio_pads,
- gpio_cfg[board_type].num_pads);
- }
+ setup_iomux_gpio(board_type, &ventana_info);
return 0;
}
return 0;
/* Display GSC firmware revision/CRC/status */
- i2c_set_bus_num(I2C_GSC);
- if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) {
- printf("GSC: v%d", buf[0]);
- if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) {
- printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */
- printf(" 0x%02x", buf[0]); /* irq status */
- }
- puts("\n");
- }
+ gsc_info(0);
+
/* Display RTC */
if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
printf("RTC: %d\n",
int misc_init_r(void)
{
struct ventana_board_info *info = &ventana_info;
- unsigned char reg;
/* set env vars based on EEPROM data */
if (ventana_info.model[0]) {
* env scripts will try loading each from most specific to
* least.
*/
- if (is_cpu_type(MXC_CPU_MX6Q))
+ if (is_cpu_type(MXC_CPU_MX6Q) ||
+ is_cpu_type(MXC_CPU_MX6D))
cputype = "imx6q";
- else if (is_cpu_type(MXC_CPU_MX6DL))
+ else if (is_cpu_type(MXC_CPU_MX6DL) ||
+ is_cpu_type(MXC_CPU_MX6SOLO))
cputype = "imx6dl";
+ setenv("soctype", cputype);
+ if (8 << (ventana_info.nand_flash_size-1) >= 2048)
+ setenv("flash_layout", "large");
+ else
+ setenv("flash_layout", "normal");
memset(str, 0, sizeof(str));
for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
str[i] = tolower(info->model[i]);
- if (!getenv("model"))
- setenv("model", str);
+ setenv("model", str);
if (!getenv("fdt_file")) {
sprintf(fdt, "%s-%s.dtb", cputype, str);
setenv("fdt_file", fdt);
*p++ = 0;
setenv("model_base", str);
- if (!getenv("fdt_file1")) {
- sprintf(fdt, "%s-%s.dtb", cputype, str);
- setenv("fdt_file1", fdt);
- }
- str[4] = 'x';
+ sprintf(fdt, "%s-%s.dtb", cputype, str);
+ setenv("fdt_file1", fdt);
+ if (board_type != GW551x && board_type != GW552x)
+ str[4] = 'x';
str[5] = 'x';
str[6] = 0;
- if (!getenv("fdt_file2")) {
- sprintf(fdt, "%s-%s.dtb", cputype, str);
- setenv("fdt_file2", fdt);
- }
+ sprintf(fdt, "%s-%s.dtb", cputype, str);
+ setenv("fdt_file2", fdt);
}
/* initialize env from EEPROM */
/* board serial-number */
sprintf(str, "%6d", info->serial);
setenv("serial#", str);
+
+ /* memory MB */
+ sprintf(str, "%d", (int) (gd->ram_size >> 20));
+ setenv("mem_mb", str);
}
- /* setup baseboard specific GPIO pinmux and config */
- setup_board_gpio(board_type);
+ /* setup baseboard specific GPIO based on board and env */
+ setup_board_gpio(board_type, info);
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
- /*
- * The Gateworks System Controller implements a boot
- * watchdog (always enabled) as a workaround for IMX6 boot related
- * errata such as:
- * ERR005768 - no fix
- * ERR006282 - fixed in silicon r1.3
- * ERR007117 - fixed in silicon r1.3
- * ERR007220 - fixed in silicon r1.3
- * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
- *
- * Disable the boot watchdog and display/clear the timeout flag if set
- */
- i2c_set_bus_num(I2C_GSC);
- if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) {
- reg |= (1 << GSC_SC_CTRL1_WDDIS);
- if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
- puts("Error: could not disable GSC Watchdog\n");
- } else {
- puts("Error: could not disable GSC Watchdog\n");
- }
- if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1)) {
- if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */
- puts("GSC boot watchdog timeout detected");
- reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */
- gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1);
- }
- }
+ /* disable boot watchdog */
+ gsc_boot_wd_disable();
return 0;
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-/* FDT aliases associated with EEPROM config bits */
-const char *fdt_aliases[] = {
- "ethernet0",
- "ethernet1",
- "hdmi_out",
- "ahci0",
- "pcie",
- "ssi0",
- "ssi1",
- "lcd0",
- "lvds0",
- "lvds1",
- "usb0",
- "usb1",
- "mmc0",
- "mmc1",
- "mmc2",
- "mmc3",
- "uart0",
- "uart1",
- "uart2",
- "uart3",
- "uart4",
- "ipu0",
- "ipu1",
- "can0",
- "mipi_dsi",
- "mipi_csi",
- "tzasc0",
- "tzasc1",
- "i2c0",
- "i2c1",
- "i2c2",
- "vpu",
- "csi0",
- "csi1",
- "caam",
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- "spi0",
- "spi1",
- "spi2",
- "spi3",
- "spi4",
- "spi5",
- NULL,
- NULL,
- "pps",
- NULL,
- NULL,
- NULL,
- "hdmi_in",
- "cvbs_out",
- "cvbs_in",
- "nand",
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
-};
+static int ft_sethdmiinfmt(void *blob, char *mode)
+{
+ int off;
+
+ if (!mode)
+ return -EINVAL;
+
+ off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
+ if (off < 0)
+ return off;
+
+ if (0 == strcasecmp(mode, "yuv422bt656")) {
+ u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
+ 0x00, 0x00, 0x00 };
+ mode = "422_ccir";
+ fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
+ fdt_setprop_u32(blob, off, "vidout_trc", 1);
+ fdt_setprop_u32(blob, off, "vidout_blc", 1);
+ fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
+ printf(" set HDMI input mode to %s\n", mode);
+ } else if (0 == strcasecmp(mode, "yuv422smp")) {
+ u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
+ 0x82, 0x81, 0x00 };
+ mode = "422_smp";
+ fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
+ fdt_setprop_u32(blob, off, "vidout_trc", 0);
+ fdt_setprop_u32(blob, off, "vidout_blc", 0);
+ fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
+ printf(" set HDMI input mode to %s\n", mode);
+ } else {
+ return -EINVAL;
+ }
+
+ return 0;
+}
/*
* called prior to booting kernel or by 'fdt boardsetup' command
* - board (full model from EEPROM)
* - peripherals removed from DTB if not loaded on board (per EEPROM config)
*/
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
- int bit;
struct ventana_board_info *info = &ventana_info;
+ struct ventana_eeprom_config *cfg;
struct node_info nodes[] = {
{ "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
{ "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
};
const char *model = getenv("model");
+ const char *display = getenv("display");
+ int i;
+ char rev = 0;
+
+ /* determine board revision */
+ for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
+ if (ventana_info.model[i] >= 'A') {
+ rev = ventana_info.model[i];
+ break;
+ }
+ }
if (getenv("fdt_noauto")) {
puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
- return;
+ return 0;
}
- /* Update partition nodes using info from mtdparts env var */
- puts(" Updating MTD partitions...\n");
- fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+ if (test_bit(EECONFIG_NAND, info->config)) {
+ /* Update partition nodes using info from mtdparts env var */
+ puts(" Updating MTD partitions...\n");
+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+ }
- if (!model) {
- puts("invalid board info: Leaving FDT fully enabled\n");
- return;
+ /* Update display timings from display env var */
+ if (display) {
+ if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
+ display) >= 0)
+ printf(" Set display timings for %s...\n", display);
}
+
printf(" Adjusting FDT per EEPROM for %s...\n", model);
/* board serial number */
fdt_setprop(blob, 0, "board", info->model,
strlen((const char *)info->model) + 1);
+ /* set desired digital video capture format */
+ ft_sethdmiinfmt(blob, getenv("hdmiinfmt"));
+
+ /*
+ * disable serial2 node for GW54xx for compatibility with older
+ * 3.10.x kernel that improperly had this node enabled in the DT
+ */
+ if (board_type == GW54xx) {
+ i = fdt_path_offset(blob,
+ "/soc/aips-bus@02100000/serial@021ec000");
+ if (i)
+ fdt_del_node(blob, i);
+ }
+
+ /*
+ * disable wdog1/wdog2 nodes for GW51xx below revC to work around
+ * errata causing wdog timer to be unreliable.
+ */
+ if (board_type == GW51xx && rev >= 'A' && rev < 'C') {
+ i = fdt_path_offset(blob,
+ "/soc/aips-bus@02000000/wdog@020bc000");
+ if (i)
+ fdt_status_disabled(blob, i);
+ }
+
+ /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
+ else if (board_type == GW52xx && info->model[4] == '2') {
+ u32 handle = 0;
+ u32 *range = NULL;
+
+ i = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
+ if (i)
+ range = (u32 *)fdt_getprop(blob, i, "reset-gpio",
+ NULL);
+
+ if (range) {
+ i = fdt_path_offset(blob,
+ "/soc/aips-bus@02000000/gpio@020a4000");
+ if (i)
+ handle = fdt_get_phandle(blob, i);
+ if (handle) {
+ range[0] = cpu_to_fdt32(handle);
+ range[1] = cpu_to_fdt32(23);
+ }
+ }
+ }
+
+ /*
+ * isolate CSI0_DATA_EN for GW551x below revB to work around
+ * errata causing non functional digital video in (it is not hooked up)
+ */
+ else if (board_type == GW551x && rev == 'A') {
+ u32 *range = NULL;
+ int len;
+ const u32 *handle = NULL;
+
+ i = fdt_node_offset_by_compatible(blob, -1,
+ "fsl,imx-tda1997x-video");
+ if (i)
+ handle = fdt_getprop(blob, i, "pinctrl-0", NULL);
+ if (handle)
+ i = fdt_node_offset_by_phandle(blob,
+ fdt32_to_cpu(*handle));
+ if (i)
+ range = (u32 *)fdt_getprop(blob, i, "fsl,pins", &len);
+ if (range) {
+ len /= sizeof(u32);
+ for (i = 0; i < len; i += 6) {
+ u32 mux_reg = fdt32_to_cpu(range[i+0]);
+ u32 conf_reg = fdt32_to_cpu(range[i+1]);
+ /* mux PAD_CSI0_DATA_EN to GPIO */
+ if (is_cpu_type(MXC_CPU_MX6Q) &&
+ mux_reg == 0x260 && conf_reg == 0x630)
+ range[i+3] = cpu_to_fdt32(0x5);
+ else if (!is_cpu_type(MXC_CPU_MX6Q) &&
+ mux_reg == 0x08c && conf_reg == 0x3a0)
+ range[i+3] = cpu_to_fdt32(0x5);
+ }
+ fdt_setprop_inplace(blob, i, "fsl,pins", range, len);
+ }
+
+ /* set BT656 video format */
+ ft_sethdmiinfmt(blob, "yuv422bt656");
+ }
+
/*
* Peripheral Config:
* remove nodes by alias path if EEPROM config tells us the
* peripheral is not loaded on the board.
*/
- for (bit = 0; bit < 64; bit++) {
- if (!test_bit(bit, info->config))
- fdt_del_node_and_alias(blob, fdt_aliases[bit]);
+ if (getenv("fdt_noconfig")) {
+ puts(" Skiping periperhal config (fdt_noconfig defined)\n");
+ return 0;
}
+ cfg = econfig;
+ while (cfg->name) {
+ if (!test_bit(cfg->bit, info->config)) {
+ fdt_del_node_and_alias(blob, cfg->dtalias ?
+ cfg->dtalias : cfg->name);
+ }
+ cfg++;
+ }
+
+ return 0;
}
#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
+static struct mxc_serial_platdata ventana_mxc_serial_plat = {
+ .reg = (struct mxc_uart *)UART2_BASE,
+};
+
+U_BOOT_DEVICE(ventana_serial) = {
+ .name = "serial_mxc",
+ .platdata = &ventana_mxc_serial_plat,
+};
projects / platform / kernel / u-boot.git / blobdiff