Merge tag 'video-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-video into...

[platform/kernel/u-boot.git] / board / freescale / t1040qds / ddr.c

diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c
index 4fd17da..0a817d0 100644 (file)
--- a/board/freescale/t1040qds/ddr.c
+++ b/board/freescale/t1040qds/ddr.c
@@ -1,16 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
  */
 
 #include <common.h>
 #include <i2c.h>
 #include <hwconfig.h>
+#include <init.h>
+#include <log.h>
 #include <asm/mmu.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 #include <asm/fsl_law.h>
+#include <asm/mpc85xx_gpio.h>
+#include <linux/delay.h>
 #include "ddr.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -39,14 +42,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
                if (pbsp->n_ranks == pdimm->n_ranks &&
                    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
                        if (ddr_freq <= pbsp->datarate_mhz_high) {
-                               popts->cpo_override = pbsp->cpo;
-                               popts->write_data_delay =
-                                       pbsp->write_data_delay;
                                popts->clk_adjust = pbsp->clk_adjust;
                                popts->wrlvl_start = pbsp->wrlvl_start;
                                popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
                                popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-                               popts->twot_en = pbsp->force_2t;
                                goto found;
                        }
                        pbsp_highest = pbsp;
@@ -59,13 +58,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
                printf("for data rate %lu MT/s\n", ddr_freq);
                printf("Trying to use the highest speed (%u) parameters\n",
                       pbsp_highest->datarate_mhz_high);
-               popts->cpo_override = pbsp_highest->cpo;
-               popts->write_data_delay = pbsp_highest->write_data_delay;
                popts->clk_adjust = pbsp_highest->clk_adjust;
                popts->wrlvl_start = pbsp_highest->wrlvl_start;
                popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
                popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-               popts->twot_en = pbsp_highest->force_2t;
        } else {
                panic("DIMM is not supported by this board");
        }
@@ -81,7 +77,7 @@ found:
         * Factors to consider for half-strength driver enable:
         *      - number of DIMMs installed
         */
-       popts->half_strength_driver_enable = 0;
+       popts->half_strength_driver_enable = 1;
        /*
         * Write leveling override
         */
@@ -97,11 +93,33 @@ found:
        popts->zq_en = 1;
 
        /* DHC_EN =1, ODT = 75 Ohm */
+#ifdef CONFIG_SYS_FSL_DDR4
+       popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+       popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+                         DDR_CDR2_VREF_OVRD(70);       /* Vref = 70% */
+
+       /* optimize cpo for erratum A-009942 */
+       popts->cpo_sample = 0x69;
+#else
        popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
        popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
 }
 
-phys_size_t initdram(int board_type)
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+       void __iomem *qixis_base = (void *)QIXIS_BASE;
+
+       /* does not provide HW signals for power management */
+       clrbits_8(qixis_base + 0x21, 0x2);
+       /* Disable MCKE isolation */
+       gpio_set_value(2, 0);
+       udelay(1);
+}
+#endif
+
+int dram_init(void)
 {
        phys_size_t dram_size;
 
@@ -113,5 +131,12 @@ phys_size_t initdram(int board_type)
        dram_size *= 0x100000;
 
        puts("    DDR: ");
-       return dram_size;
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+       fsl_dp_resume();
+#endif
+
+       gd->ram_size = dram_size;
+
+       return 0;
 }