Merge tag 'video-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-video into...

[platform/kernel/u-boot.git] / board / freescale / t102xqds / ddr.c

diff --git a/board/freescale/t102xqds/ddr.c b/board/freescale/t102xqds/ddr.c
index 2d4d10f..c27cecd 100644 (file)
--- a/board/freescale/t102xqds/ddr.c
+++ b/board/freescale/t102xqds/ddr.c
@@ -1,17 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <i2c.h>
 #include <hwconfig.h>
+#include <init.h>
+#include <log.h>
 #include <asm/mmu.h>
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr_dimm_params.h>
 #include <asm/fsl_law.h>
 #include <asm/mpc85xx_gpio.h>
+#include <linux/delay.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -35,18 +37,18 @@ static const struct board_specific_parameters udimm0[] = {
         * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
         */
 #if defined(CONFIG_SYS_FSL_DDR4)
-       {2,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
-       {2,  1900,  0,  4,  6,  0x08080A0C,  0x0D0E0F0A,},
-       {1,  1666,  0,  4,  6,  0x0708090B,  0x0C0D0E09,},
-       {1,  1900,  0,  4,  6,  0x08080A0C,  0x0D0E0F0A,},
-       {1,  2200,  0,  4,  7,  0x08090A0D,  0x0F0F100C,},
+       {2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
+       {2,  1900,  0,  8,  6,  0x08080A0C,  0x0D0E0F0A,},
+       {1,  1666,  0,  8,  6,  0x0708090B,  0x0C0D0E09,},
+       {1,  1900,  0,  8,  6,  0x08080A0C,  0x0D0E0F0A,},
+       {1,  2200,  0,  8,  7,  0x08090A0D,  0x0F0F100C,},
 #elif defined(CONFIG_SYS_FSL_DDR3)
-       {2,  833,   0,  4,  6,  0x06060607,  0x08080807,},
-       {2,  1350,  0,  4,  7,  0x0708080A,  0x0A0B0C09,},
-       {2,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
-       {1,  833,   0,  4,  6,  0x06060607,  0x08080807,},
-       {1,  1350,  0,  4,  7,  0x0708080A,  0x0A0B0C09,},
-       {1,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
+       {2,  833,   0,  8,  6,  0x06060607,  0x08080807,},
+       {2,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
+       {2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
+       {1,  833,   0,  8,  6,  0x06060607,  0x08080807,},
+       {1,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
+       {1,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
 #else
 #error DDR type not defined
 #endif
@@ -139,6 +141,9 @@ found:
 #else
        popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
        popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+
+       /* optimize cpo for erratum A-009942 */
+       popts->cpo_sample = 0x5f;
 #endif
 
        /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
@@ -166,24 +171,25 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
        phys_size_t dram_size;
 
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
        puts("Initializing....using SPD\n");
-
        dram_size = fsl_ddr_sdram();
-       dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-       dram_size *= 0x100000;
 #else
        /* DDR has been initialised by first stage boot loader */
        dram_size =  fsl_ddr_sdram_size();
 #endif
+       dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+       dram_size *= 0x100000;
 
 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
        fsl_dp_resume();
 #endif
 
-       return dram_size;
+       gd->ram_size = dram_size;
+
+       return 0;
 }