global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace

[platform/kernel/u-boot.git] / board / freescale / p2041rdb / p2041rdb.c

diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index 78ee747..1b12630 100644 (file)
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -1,12 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2011,2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <command.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <image.h>
+#include <init.h>
 #include <netdev.h>
+#include <asm/global_data.h>
 #include <linux/compiler.h>
 #include <asm/mmu.h>
 #include <asm/processor.h>
@@ -17,7 +22,7 @@
 #include <asm/fsl_liodn.h>
 #include <fm_eth.h>
 
-extern void pci_of_setup(void *blob, bd_t *bd);
+extern void pci_of_setup(void *blob, struct bd_info *bd);
 
 #include "cpld.h"
 
@@ -61,7 +66,7 @@ int checkboard(void)
 
 int board_early_init_f(void)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
        /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */
        setbits_be32(&gur->ddrclkdr, 0x000f000f);
@@ -76,7 +81,7 @@ int board_early_init_f(void)
 
 void board_config_lanes_mux(void)
 {
-       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
        int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
                                FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
 
@@ -144,7 +149,7 @@ int board_early_init_r(void)
        return 0;
 }
 
-unsigned long get_board_sys_clk(unsigned long dummy)
+unsigned long get_board_sys_clk(void)
 {
        u8 sysclk_conf = CPLD_READ(sysclk_sw1);
 
@@ -162,7 +167,7 @@ unsigned long get_board_sys_clk(unsigned long dummy)
 
 int misc_init_r(void)
 {
-       serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+       serdes_corenet_t *regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
        u32 actual[NUM_SRDS_BANKS];
        unsigned int i;
        u8 sw;
@@ -212,7 +217,7 @@ int misc_init_r(void)
        return 0;
 }
 
-int ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, struct bd_info *bd)
 {
        phys_addr_t base;
        phys_size_t size;
@@ -224,7 +229,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 
        fdt_fixup_memory(blob, (u64)base, (u64)size);
 
-#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
+#if defined(CONFIG_HAS_FSL_DR_USB)
        fsl_fdt_fixup_dr_usb(blob, bd);
 #endif
 
@@ -234,8 +239,10 @@ int ft_board_setup(void *blob, bd_t *bd)
 
        fdt_fixup_liodn(blob);
 #ifdef CONFIG_SYS_DPAA_FMAN
+#ifndef CONFIG_DM_ETH
        fdt_fixup_fman_ethernet(blob);
 #endif
+#endif
 
        return 0;
 }