board: freescale: powerpc: add support for all RGMII modes

[platform/kernel/u-boot.git] / board / freescale / p2041rdb / eth.c

diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c
index 3969816..23fd619 100644 (file)
--- a/board/freescale/p2041rdb/eth.c
+++ b/board/freescale/p2041rdb/eth.c
@@ -81,17 +81,21 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 {
        phy_interface_t intf = fm_info_get_enet_if(port);
        char phy[16];
+       int lane;
+       u8 slot;
 
+       switch (intf) {
        /* The RGMII PHY is identified by the MAC connected to it */
-       if (intf == PHY_INTERFACE_MODE_RGMII) {
+       case PHY_INTERFACE_MODE_RGMII:
+       case PHY_INTERFACE_MODE_RGMII_TXID:
+       case PHY_INTERFACE_MODE_RGMII_RXID:
+       case PHY_INTERFACE_MODE_RGMII_ID:
                sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1);
                fdt_set_phy_handle(fdt, compat, addr, phy);
-       }
-
+               break;
        /* The SGMII PHY is identified by the MAC connected to it */
-       if (intf == PHY_INTERFACE_MODE_SGMII) {
-               int lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port);
-               u8 slot;
+       case PHY_INTERFACE_MODE_SGMII:
+               lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port);
                if (lane < 0)
                        return;
                slot = lane_to_slot[lane];
@@ -106,16 +110,18 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
                                        + (port - FM1_DTSEC1));
                        fdt_set_phy_handle(fdt, compat, addr, phy);
                }
-       }
-
-       if (intf == PHY_INTERFACE_MODE_XGMII) {
+               break;
+       case PHY_INTERFACE_MODE_XGMII:
                /* XAUI */
-               int lane = serdes_get_first_lane(XAUI_FM1);
+               lane = serdes_get_first_lane(XAUI_FM1);
                if (lane >= 0) {
                        /* The XAUI PHY is identified by the slot */
                        sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
                        fdt_set_phy_handle(fdt, compat, addr, phy);
                }
+               break;
+       default:
+               break;
        }
 }
 #endif /* #ifdef CONFIG_FMAN_ENET */
@@ -169,6 +175,9 @@ int board_eth_init(struct bd_info *bis)
                                fm_info_set_phy_address(i, riser_phy_addr[i]);
                        break;
                case PHY_INTERFACE_MODE_RGMII:
+               case PHY_INTERFACE_MODE_RGMII_TXID:
+               case PHY_INTERFACE_MODE_RGMII_RXID:
+               case PHY_INTERFACE_MODE_RGMII_ID:
                        /* Only DTSEC4 and DTSEC5 can be routed to RGMII */
                        fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
                                        CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :