ppc: Remove corenet_ds boards

[platform/kernel/u-boot.git] / board / freescale / p2041rdb / cpld.c

diff --git a/board/freescale/p2041rdb/cpld.c b/board/freescale/p2041rdb/cpld.c
index a4bcc18..a1908b8 100644 (file)
--- a/board/freescale/p2041rdb/cpld.c
+++ b/board/freescale/p2041rdb/cpld.c
@@ -1,19 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
 /**
  * Copyright 2011 Freescale Semiconductor
  * Author: Mingkai Hu <Mingkai.hu@freescale.com>
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
  * This file provides support for the board-specific CPLD used on some Freescale
  * reference boards.
  *
  * The following macros need to be defined:
  *
  * CPLD_BASE - The virtual address of the base of the CPLD register map
- *
  */
 
 #include <common.h>
@@ -92,7 +87,7 @@ static void cpld_dump_regs(void)
 }
 #endif
 
-int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int cpld_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 {
        int rc = 0;
 
@@ -105,8 +100,8 @@ int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
                else
                        cpld_set_defbank();
        } else if (strcmp(argv[1], "lane_mux") == 0) {
-               u32 lane = simple_strtoul(argv[2], NULL, 16);
-               u8 val = (u8)simple_strtoul(argv[3], NULL, 16);
+               u32 lane = hextoul(argv[2], NULL);
+               u8 val = (u8)hextoul(argv[3], NULL);
                u8 reg = CPLD_READ(serdes_mux);
 
                switch (lane) {