#include <asm/mp.h>
#include <netdev.h>
-#include "../common/pixis.h"
+#include "../common/ngpixis.h"
#include "../common/sgmii_riser.h"
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
+ u8 sw;
+
puts("Board: P2020DS ");
#ifdef CONFIG_PHYS_64BIT
puts("(36-bit addrmap) ");
#endif
- printf("Sys ID: 0x%02x, "
- "Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n",
- in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
- in8(PIXIS_BASE + PIXIS_PVER));
+
+ printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+ in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
+
+ sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
+ sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
+
+ if (sw < 0x8)
+ /* The lower two bits are the actual vbank number */
+ printf("vBank: %d\n", sw & 3);
+ else
+ puts("Promjet\n");
+
return 0;
}
static struct pci_controller pcie3_hose;
#endif
-int first_free_busno = 0;
-
#ifdef CONFIG_PCI
void pci_init_board(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- uint devdisr = gur->devdisr;
- uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+ struct fsl_pci_info pci_info[3];
+ u32 devdisr, pordevsr, io_sel;
+ int first_free_busno = 0;
+ int num = 0;
- volatile ccsr_fsl_pci_t *pci;
- struct pci_controller *hose;
int pcie_ep, pcie_configured;
- struct pci_region *r;
-/* u32 temp32; */
- debug(" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
- devdisr, io_sel, host_agent);
+ devdisr = in_be32(&gur->devdisr);
+ pordevsr = in_be32(&gur->pordevsr);
+ io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
+ debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
+
+ if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
printf(" eTSEC2 is in sgmii mode.\n");
- if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
+ if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
printf(" eTSEC3 is in sgmii mode.\n");
+ puts("\n");
#ifdef CONFIG_PCIE2
- pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
- hose = &pcie2_hose;
- pcie_ep = (host_agent == 2) || (host_agent == 4) ||
- (host_agent == 6) || (host_agent == 0);
- pcie_configured = (io_sel == 0x2) || (io_sel == 0xe);
- r = hose->regions;
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
- printf("\n PCIE2 connected to ULI as %s (base addr %x)",
- pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug(" with errors. Clearing. Now 0x%08x",
- pci->pme_msg_det);
- }
- printf("\n");
-
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE2_MEM_BUS,
- CONFIG_SYS_PCIE2_MEM_PHYS,
- CONFIG_SYS_PCIE2_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE2_IO_BUS,
- CONFIG_SYS_PCIE2_IO_PHYS,
- CONFIG_SYS_PCIE2_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
- hose->first_busno = first_free_busno;
- pci_setup_indirect(hose, (int)&pci->cfg_addr,
- (int)&pci->cfg_data);
-
- fsl_pci_init(hose);
- first_free_busno = hose->last_busno+1;
- printf(" PCIE2 on bus %02x - %02x\n",
- hose->first_busno, hose->last_busno);
+ SET_STD_PCIE_INFO(pci_info[num], 2);
+ pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
+ printf(" PCIE2 connected to ULI as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie2_hose, first_free_busno);
/*
* The workaround doesn't work on p2020 because the location
} else {
printf(" PCIE2: disabled\n");
}
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
#endif
#ifdef CONFIG_PCIE3
- pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
- hose = &pcie3_hose;
- pcie_ep = (host_agent == 0) || (host_agent == 3) ||
- (host_agent == 5) || (host_agent == 6);
- pcie_configured = (io_sel == 0x2) || (io_sel == 0x4);
- r = hose->regions;
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
- printf("\n PCIE3 connected to Slot 1 as %s (base addr %x)",
- pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug(" with errors. Clearing. Now 0x%08x",
- pci->pme_msg_det);
- }
- printf("\n");
-
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE3_MEM_BUS,
- CONFIG_SYS_PCIE3_MEM_PHYS,
- CONFIG_SYS_PCIE3_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE3_IO_BUS,
- CONFIG_SYS_PCIE3_IO_PHYS,
- CONFIG_SYS_PCIE3_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
- hose->first_busno = first_free_busno;
- pci_setup_indirect(hose, (int)&pci->cfg_addr,
- (int)&pci->cfg_data);
-
- fsl_pci_init(hose);
-
- first_free_busno = hose->last_busno+1;
- printf(" PCIE3 on bus %02x - %02x\n",
- hose->first_busno, hose->last_busno);
-
+ SET_STD_PCIE_INFO(pci_info[num], 3);
+ pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
+ printf(" PCIE3 connected to Slot 1 as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie3_hose, first_free_busno);
} else {
printf(" PCIE3: disabled\n");
}
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
#endif
#ifdef CONFIG_PCIE1
- pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- hose = &pcie1_hose;
- pcie_ep = (host_agent <= 1) || (host_agent == 4) || (host_agent == 5);
- pcie_configured = (io_sel & 6) || (io_sel == 0xE) || (io_sel == 0xF);
- r = hose->regions;
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
- printf("\n PCIE1 connected to Slot 2 as %s (base addr %x)",
- pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug(" with errors. Clearing. Now 0x%08x",
- pci->pme_msg_det);
- }
- printf("\n");
-
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BUS,
- CONFIG_SYS_PCIE1_MEM_PHYS,
- CONFIG_SYS_PCIE1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BUS,
- CONFIG_SYS_PCIE1_IO_PHYS,
- CONFIG_SYS_PCIE1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
- hose->first_busno = first_free_busno;
-
- pci_setup_indirect(hose, (int)&pci->cfg_addr,
- (int)&pci->cfg_data);
-
- fsl_pci_init(hose);
-
- first_free_busno = hose->last_busno+1;
- printf(" PCIE1 on bus %02x - %02x\n",
- hose->first_busno, hose->last_busno);
-
+ SET_STD_PCIE_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+ printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie1_hose, first_free_busno);
} else {
printf(" PCIE1: disabled\n");
}
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
#endif
}
#endif
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- const u8 flash_esel = 2;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
return gd->mem_clk;
}
-unsigned long
-calculate_board_sys_clk(ulong dummy)
+unsigned long calculate_board_sys_clk(ulong dummy)
{
ulong val;
- val = ics307_clk_freq(
- in8(PIXIS_BASE + PIXIS_VSYSCLK0),
- in8(PIXIS_BASE + PIXIS_VSYSCLK1),
- in8(PIXIS_BASE + PIXIS_VSYSCLK2));
+
+ val = ics307_clk_freq(in_8(&pixis->sclk[0]), in_8(&pixis->sclk[1]),
+ in_8(&pixis->sclk[2]));
debug("sysclk val = %lu\n", val);
return val;
}
-unsigned long
-calculate_board_ddr_clk(ulong dummy)
+unsigned long calculate_board_ddr_clk(ulong dummy)
{
ulong val;
- val = ics307_clk_freq(
- in8(PIXIS_BASE + PIXIS_VDDRCLK0),
- in8(PIXIS_BASE + PIXIS_VDDRCLK1),
- in8(PIXIS_BASE + PIXIS_VDDRCLK2));
+
+ val = ics307_clk_freq(in_8(&pixis->dclk[0]), in_8(&pixis->dclk[1]),
+ in_8(&pixis->dclk[2]));
debug("ddrclk val = %lu\n", val);
return val;
}
u8 i;
ulong val = 0;
- i = in8(PIXIS_BASE + PIXIS_SPD);
+ i = in_8(&pixis->spd);
i &= 0x07;
switch (i) {
u8 i;
ulong val = 0;
- i = in8(PIXIS_BASE + PIXIS_SPD);
+ i = in_8(&pixis->spd);
i &= 0x38;
i >>= 3;
projects / platform / kernel / u-boot.git / blobdiff