/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
* Timur Tabi <timur@freescale.com>
*
/* Set pmuxcr to allow both i2c1 and i2c2 */
setbits_be32(&gur->pmuxcr, 0x1000);
+#ifdef CONFIG_SYS_RAMBOOT
+ setbits_be32(&gur->pmuxcr,
+ in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
+#endif
/* Read back the register to synchronize the write. */
in_be32(&gur->pmuxcr);
{
u8 sw;
- puts("Board: P1022DS ");
-#ifdef CONFIG_PHYS_64BIT
- puts("(36-bit addrmap) ");
-#endif
-
- printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+ printf("Board: P1022DS Sys ID: 0x%02x, "
+ "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
* ft_codec_setup - fix up the clock-frequency property of the codec node
*
* Update the clock-frequency property based on the value of the 'audclk'
- * hwconfig option. If audclk is not specified, then default to 12.288MHz.
+ * hwconfig option. If audclk is not specified, then don't write anything
+ * to the device tree, because it means that the codec clock is disabled.
*/
static void ft_codec_setup(void *blob, const char *compatible)
{
u32 freq;
audclk = hwconfig_arg("audclk", &arglen);
- if (audclk && (strncmp(audclk, "11", 2) == 0))
- freq = 11289600;
- else
- freq = 12288000;
+ if (audclk) {
+ if (strncmp(audclk, "11", 2) == 0)
+ freq = 11289600;
+ else
+ freq = 12288000;
- do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1);
+ do_fixup_by_compat_u32(blob, compatible, "clock-frequency",
+ freq, 1);
+ }
}
void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory(blob, (u64)base, (u64)size);
+#ifdef CONFIG_HAS_FSL_DR_USB
+ fdt_fixup_dr_usb(blob, bd);
+#endif
+
FT_FSL_PCI_SETUP;
#ifdef CONFIG_FSL_SGMII_RISER