mx6qsabresd: Add Ethernet support

[platform/kernel/u-boot.git] / board / freescale / mx6qsabresd / mx6qsabresd.c

diff --git a/board/freescale/mx6qsabresd/mx6qsabresd.c b/board/freescale/mx6qsabresd/mx6qsabresd.c
index c86b51b..069c664 100644 (file)
--- a/board/freescale/mx6qsabresd/mx6qsabresd.c
+++ b/board/freescale/mx6qsabresd/mx6qsabresd.c
@@ -56,6 +56,36 @@ iomux_v3_cfg_t uart1_pads[] = {
        MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
+iomux_v3_cfg_t enet_pads[] = {
+       MX6Q_PAD_ENET_MDIO__ENET_MDIO           | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6Q_PAD_ENET_MDC__ENET_MDC             | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC      | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0      | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1      | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2      | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3      | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL     | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK      | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC      | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0      | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1      | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2      | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3      | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL     | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       /* AR8031 PHY Reset */
+       MX6Q_PAD_ENET_CRS_DV__GPIO_1_25         | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+       imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+       /* Reset AR8031 PHY */
+       gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
+       udelay(500);
+       gpio_set_value(IMX_GPIO_NR(1, 25), 1);
+}
+
 iomux_v3_cfg_t usdhc3_pads[] = {
        MX6Q_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6Q_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -90,6 +120,52 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+       unsigned short val;
+
+       /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+       phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+       phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+       phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+       val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+       val &= 0xffe3;
+       val |= 0x18;
+       phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+       /* introduce tx clock delay */
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+       val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+       val |= 0x0100;
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+       return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+       mx6_rgmii_rework(phydev);
+
+       if (phydev->drv->config)
+               phydev->drv->config(phydev);
+
+       return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+       int ret;
+
+       setup_iomux_enet();
+
+       ret = cpu_eth_init(bis);
+       if (ret)
+               printf("FEC MXC: %s:failed\n", __func__);
+
+       return 0;
+}
+
 u32 get_board_rev(void)
 {
        return 0x63000;