#include <common.h>
#include <asm/io.h>
+#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx5x_pins.h>
#include <asm/arch/iomux.h>
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
+#include <pmic.h>
#include <fsl_pmic.h>
#include <mc13892.h>
int dram_init(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
- PHYS_SDRAM_1_SIZE);
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
return 0;
}
static void power_init(void)
{
unsigned int val;
- unsigned int reg;
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+ struct pmic *p;
+
+ pmic_init();
+ p = get_pmic();
/* Write needed to Power Gate 2 register */
- val = pmic_reg_read(REG_POWER_MISC);
+ pmic_reg_read(p, REG_POWER_MISC, &val);
val &= ~PWGT2SPIEN;
- pmic_reg_write(REG_POWER_MISC, val);
+ pmic_reg_write(p, REG_POWER_MISC, val);
- /* Write needed to update Charger 0 */
- pmic_reg_write(REG_CHARGE, VCHRG0 | VCHRG1 | VCHRG2 |
- ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | ICHRGTR0 |
- OVCTRL1 | UCHEN | CHRGLEDEN | CYCLB);
+ /* Externally powered */
+ pmic_reg_read(p, REG_CHARGE, &val);
+ val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
+ pmic_reg_write(p, REG_CHARGE, val);
/* power up the system first */
- pmic_reg_write(REG_POWER_MISC, PWUP);
+ pmic_reg_write(p, REG_POWER_MISC, PWUP);
/* Set core voltage to 1.1V */
- val = pmic_reg_read(REG_SW_0);
- val = (val & (~0x1F)) | 0x14;
- pmic_reg_write(REG_SW_0, val);
+ pmic_reg_read(p, REG_SW_0, &val);
+ val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
+ pmic_reg_write(p, REG_SW_0, val);
/* Setup VCC (SW2) to 1.25 */
- val = pmic_reg_read(REG_SW_1);
- val = (val & (~0x1F)) | 0x1A;
- pmic_reg_write(REG_SW_1, val);
+ pmic_reg_read(p, REG_SW_1, &val);
+ val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
+ pmic_reg_write(p, REG_SW_1, val);
/* Setup 1V2_DIG1 (SW3) to 1.25 */
- val = pmic_reg_read(REG_SW_2);
- val = (val & (~0x1F)) | 0x1A;
- pmic_reg_write(REG_SW_2, val);
+ pmic_reg_read(p, REG_SW_2, &val);
+ val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
+ pmic_reg_write(p, REG_SW_2, val);
udelay(50);
/* Raise the core frequency to 800MHz */
/* Set switchers in Auto in NORMAL mode & STANDBY mode */
/* Setup the switcher mode for SW1 & SW2*/
- val = pmic_reg_read(REG_SW_4);
+ pmic_reg_read(p, REG_SW_4, &val);
val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
(SWMODE_MASK << SWMODE2_SHIFT)));
val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
- pmic_reg_write(REG_SW_4, val);
+ pmic_reg_write(p, REG_SW_4, val);
/* Setup the switcher mode for SW3 & SW4 */
- val = pmic_reg_read(REG_SW_5);
+ pmic_reg_read(p, REG_SW_5, &val);
val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
(SWMODE_MASK << SWMODE4_SHIFT)));
val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
(SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
- pmic_reg_write(REG_SW_5, val);
+ pmic_reg_write(p, REG_SW_5, val);
/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
- val = pmic_reg_read(REG_SETTING_0);
+ pmic_reg_read(p, REG_SETTING_0, &val);
val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
- pmic_reg_write(REG_SETTING_0, val);
+ pmic_reg_write(p, REG_SETTING_0, val);
/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
- val = pmic_reg_read(REG_SETTING_1);
+ pmic_reg_read(p, REG_SETTING_1, &val);
val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
- pmic_reg_write(REG_SETTING_1, val);
+ pmic_reg_write(p, REG_SETTING_1, val);
/* Configure VGEN3 and VCAM regulators to use external PNP */
val = VGEN3CONFIG | VCAMCONFIG;
- pmic_reg_write(REG_MODE_1, val);
+ pmic_reg_write(p, REG_MODE_1, val);
udelay(200);
- reg = readl(GPIO2_BASE_ADDR + 0x0);
- reg &= ~0x4000; /* Lower reset line */
- writel(reg, GPIO2_BASE_ADDR + 0x0);
-
- reg = readl(GPIO2_BASE_ADDR + 0x4);
- reg |= 0x4000; /* configure GPIO lines as output */
- writel(reg, GPIO2_BASE_ADDR + 0x4);
-
- /* Reset the ethernet controller over GPIO */
- writel(0x1, IOMUXC_BASE_ADDR + 0x0AC);
-
/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
VVIDEOEN | VAUDIOEN | VSDEN;
- pmic_reg_write(REG_MODE_1, val);
+ pmic_reg_write(p, REG_MODE_1, val);
+
+ mxc_request_iomux(MX51_PIN_EIM_A20, IOMUX_CONFIG_ALT1);
+ gpio_direction_output(46, 0);
udelay(500);
- reg = readl(GPIO2_BASE_ADDR + 0x0);
- reg |= 0x4000;
- writel(reg, GPIO2_BASE_ADDR + 0x0);
+ gpio_set_value(46, 1);
}
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
- *cd = readl(GPIO1_BASE_ADDR) & 0x01;
+ *cd = gpio_get_value(0);
else
- *cd = readl(GPIO1_BASE_ADDR) & 0x40;
+ *cd = gpio_get_value(6);
return 0;
}
}
#endif
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ setup_iomux_fec();
+
+ return 0;
+}
+
int board_init(void)
{
system_rev = get_cpu_rev();
- gd->bd->bi_arch_number = MACH_TYPE_MX51_BABBAGE;
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
- setup_iomux_uart();
- setup_iomux_fec();
-
return 0;
}
-#ifdef BOARD_LATE_INIT
+#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_MXC_SPI
int checkboard(void)
{
- puts("Board: MX51EVK ");
-
- switch (system_rev & 0xff) {
- case CHIP_REV_3_0:
- puts("3.0 [");
- break;
- case CHIP_REV_2_5:
- puts("2.5 [");
- break;
- case CHIP_REV_2_0:
- puts("2.0 [");
- break;
- case CHIP_REV_1_1:
- puts("1.1 [");
- break;
- case CHIP_REV_1_0:
- default:
- puts("1.0 [");
- break;
- }
+ puts("Board: MX51EVK\n");
- switch (__raw_readl(SRC_BASE_ADDR + 0x8)) {
- case 0x0001:
- puts("POR");
- break;
- case 0x0009:
- puts("RST");
- break;
- case 0x0010:
- case 0x0011:
- puts("WDOG");
- break;
- default:
- puts("unknown");
- }
- puts("]\n");
return 0;
}
projects / platform / kernel / u-boot.git / blobdiff