/*
- * Copyright 2008,2011 Freescale Semiconductor, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
*/
#include <common.h>
+#include <i2c.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
-struct board_specific_parameters {
- u32 n_ranks;
+static void
+get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+ i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+ return get_bus_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+ unsigned int ctrl_num)
+{
+ unsigned int i;
+ unsigned int i2c_address = 0;
+
+ for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+ if (ctrl_num == 0 && i == 0) {
+ i2c_address = SPD_EEPROM_ADDRESS1;
+ }
+ if (ctrl_num == 0 && i == 1) {
+ i2c_address = SPD_EEPROM_ADDRESS2;
+ }
+ if (ctrl_num == 1 && i == 0) {
+ i2c_address = SPD_EEPROM_ADDRESS3;
+ }
+ if (ctrl_num == 1 && i == 1) {
+ i2c_address = SPD_EEPROM_ADDRESS4;
+ }
+ get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+ }
+}
+
+typedef struct {
+ u32 datarate_mhz_low;
u32 datarate_mhz_high;
+ u32 n_ranks;
u32 clk_adjust;
u32 cpo;
u32 write_data_delay;
-};
+} board_specific_parameters_t;
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-const struct board_specific_parameters dimm0[] = {
- /*
- * memory controller 0
- * num| hi| clk| cpo|wrdata|2T
- * ranks| mhz|adjst| | delay|
- */
- {4, 333, 7, 7, 3},
- {4, 549, 7, 9, 3},
- {4, 650, 7, 10, 4},
- {2, 333, 7, 7, 3},
- {2, 549, 7, 9, 3},
- {2, 650, 7, 10, 4},
- {1, 333, 7, 7, 3},
- {1, 549, 7, 9, 3},
- {1, 650, 7, 10, 4},
- {}
-};
+/* XXX: these values need to be checked for all interleaving modes. */
+const board_specific_parameters_t board_specific_parameters[2][16] = {
+ {
+ /* memory controller 0 */
+ /* lo| hi| num| clk| cpo|wrdata */
+ /* mhz| mhz|ranks|adjst| | delay */
+ { 0, 333, 4, 7, 7, 3},
+ {334, 400, 4, 7, 9, 3},
+ {401, 549, 4, 7, 9, 3},
+ {550, 650, 4, 7, 10, 4},
-/*
- * The two slots have slightly different timing. The center values are good
- * for both slots. We use identical speed tables for them. In future use, if
- * DIMMs have fewer center values that require two separated tables, copy the
- * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
- */
-const struct board_specific_parameters *dimms[] = {
- dimm0,
- dimm0,
+ { 0, 333, 3, 7, 7, 3},
+ {334, 400, 3, 7, 9, 3},
+ {401, 549, 3, 7, 9, 3},
+ {550, 650, 3, 7, 10, 4},
+
+ { 0, 333, 2, 7, 7, 3},
+ {334, 400, 2, 7, 9, 3},
+ {401, 549, 2, 7, 9, 3},
+ {550, 650, 2, 7, 10, 4},
+
+ { 0, 333, 1, 7, 7, 3},
+ {334, 400, 1, 7, 9, 3},
+ {401, 549, 1, 7, 9, 3},
+ {550, 650, 1, 7, 10, 4}
+ },
+
+ {
+ /* memory controller 1 */
+ /* lo| hi| num| clk| cpo|wrdata */
+ /* mhz| mhz|ranks|adjst| | delay */
+ { 0, 333, 4, 7, 7, 3},
+ {334, 400, 4, 7, 9, 3},
+ {401, 549, 4, 7, 9, 3},
+ {550, 650, 4, 7, 10, 4},
+
+ { 0, 333, 3, 7, 7, 3},
+ {334, 400, 3, 7, 9, 3},
+ {401, 549, 3, 7, 9, 3},
+ {550, 650, 3, 7, 10, 4},
+
+ { 0, 333, 2, 7, 7, 3},
+ {334, 400, 2, 7, 9, 3},
+ {401, 549, 2, 7, 9, 3},
+ {550, 650, 2, 7, 10, 4},
+
+ { 0, 333, 1, 7, 7, 3},
+ {334, 400, 1, 7, 9, 3},
+ {401, 549, 1, 7, 9, 3},
+ {550, 650, 1, 7, 10, 4}
+ }
};
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- unsigned int i;
+ const board_specific_parameters_t *pbsp =
+ &(board_specific_parameters[ctrl_num][0]);
+ u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
+ sizeof(board_specific_parameters[0][0]);
+ u32 i;
+ u32 j;
ulong ddr_freq;
- if (ctrl_num > 1) {
- printf("Wrong parameter for controller number %d", ctrl_num);
- return;
- }
- for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
- if (pdimm[i].n_ranks)
- break;
+ /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
+ * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
+ * there are two dimms in the controller, set odt_rd_cfg to 3 and
+ * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
+ */
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (i&1) { /* odd CS */
+ popts->cs_local_opts[i].odt_rd_cfg = 0;
+ popts->cs_local_opts[i].odt_wr_cfg = 0;
+ } else { /* even CS */
+ if ((CONFIG_DIMM_SLOTS_PER_CTLR == 2) &&
+ (pdimm[i/2].n_ranks != 0)) {
+ popts->cs_local_opts[i].odt_rd_cfg = 3;
+ popts->cs_local_opts[i].odt_wr_cfg = 3;
+ } else {
+ popts->cs_local_opts[i].odt_rd_cfg = 0;
+ popts->cs_local_opts[i].odt_wr_cfg = 4;
+ }
+ }
}
- if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */
- return;
-
- pbsp = dimms[ctrl_num];
/* Get clk_adjust, cpo, write_data_delay, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm[i].n_ranks) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
- goto found;
+ ddr_freq = fsl_ddr_get_mem_data_rate() / 1000000;
+ for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+ if (pdimm[j].n_ranks > 0) {
+ for (i = 0; i < num_params; i++) {
+ if (ddr_freq >= pbsp->datarate_mhz_low &&
+ ddr_freq <= pbsp->datarate_mhz_high &&
+ pdimm[j].n_ranks == pbsp->n_ranks) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ break;
+ }
+ pbsp++;
}
- pbsp_highest = pbsp;
}
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found "
- "for data rate %lu MT/s!\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->cpo_override = pbsp_highest->cpo;
- popts->write_data_delay = pbsp_highest->write_data_delay;
- } else {
- panic("DIMM is not supported by this board");
}
-found:
/* 2T timing enable */
- popts->twot_en = 1;
+ popts->twoT_en = 1;
}
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