#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
#include <spd_sdram.h>
#include <i2c.h>
#include <ioports.h>
};
void local_bus_init(void);
-void sdram_init(void);
int board_early_init_f (void)
{
return 0;
}
-phys_size_t
-initdram(int board_type)
-{
- long dram_size = 0;
-
- puts("Initializing\n");
-
-#if defined(CONFIG_DDR_DLL)
- {
- /*
- * Work around to stabilize DDR DLL MSYNC_IN.
- * Errata DDR9 seems to have been fixed.
- * This is now the workaround for Errata DDR11:
- * Override DLL = 1, Course Adj = 1, Tap Select = 0
- */
-
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- gur->ddrdllcr = 0x81000000;
- asm("sync;isync;msync");
- udelay(200);
- }
-#endif
-
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- /*
- * SDRAM Initialization
- */
- sdram_init();
-
- puts(" DDR: ");
- return dram_size;
-}
-
/*
* Initialize Local Bus
*/
/*
* Initialize SDRAM memory on the Local Bus.
*/
-void
-sdram_init(void)
+void lbc_sdram_init(void)
{
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
uint lsdmr_common;
- puts(" SDRAM: ");
-
- print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+ puts("LBC SDRAM: ");
+ print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
+ "\n ");
/*
* Setup SDRAM Base and Option Registers
#endif
#ifdef CONFIG_PCIE1
- pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
+ pcie_configured = is_serdes_configured(PCIE1);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
SET_STD_PCIE_INFO(pci_info[num], 1);