#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/immap_fsl_pci.h>
-#include <spd.h>
+#include <spd_sdram.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
DECLARE_GLOBAL_DATA_PTR;
-extern long int spd_sdram(void);
-
void local_bus_init(void);
void sdram_init(void);
-int board_early_init_f (void)
-{
- return 0;
-}
-
int checkboard (void)
{
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
uint pci_slot = get_pci_slot ();
uint cpu_board_rev = get_cpu_board_revision ();
+ uint svr;
printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
get_board_version (), pci_slot);
*/
local_bus_init ();
+ svr = get_svr();
+
/*
* Fix CPU2 errata: A core hang possible while executing a
* msync instruction and a snoopable transaction from an I/O
* master tagged to make quick forward progress is present.
+ * Fixed in Silicon Rev.2.1
*/
- ecm->eebpcr |= (1 << 16);
+ if (!(SVR_MAJ(svr) >= 2 && SVR_MIN(svr) >= 1))
+ ecm->eebpcr |= (1 << 16);
/*
* Hack TSEC 3 and 4 IO voltages.
#endif /* enable SDRAM init */
}
-#if defined(CFG_DRAM_TEST)
-int
-testdram(void)
-{
- uint *pstart = (uint *) CFG_MEMTEST_START;
- uint *pend = (uint *) CFG_MEMTEST_END;
- uint *p;
-
- printf("Testing DRAM from 0x%08x to 0x%08x\n",
- CFG_MEMTEST_START,
- CFG_MEMTEST_END);
-
- printf("DRAM test phase 1:\n");
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf ("DRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("DRAM test phase 2:\n");
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf ("DRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("DRAM test passed.\n");
- return 0;
-}
-#endif
-
#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
/* For some reason the Tundra PCI bridge shows up on itself as a
* different device. Work around that by refusing to configure it.