+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
*/
#include <common.h>
+#include <fdt_support.h>
+#include <init.h>
#include <ioports.h>
#include <mpc83xx.h>
+#include <asm/bitops.h>
+#include <asm/global_data.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
#include <spi.h>
#include <miiphy.h>
-#ifdef CONFIG_FSL_DDR2
-#include <asm/fsl_ddr_sdram.h>
+#ifdef CONFIG_SYS_FSL_DDR2
+#include <fsl_ddr_sdram.h>
#else
#include <spd_sdram.h>
#endif
+#include <linux/delay.h>
#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
+#include <linux/libfdt.h>
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
int fixed_sdram(void);
void sdram_init(void);
#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
-phys_size_t initdram (int board_type)
+int dram_init(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
phys_size_t msize = 0;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
- return -1;
+ return -ENXIO;
/* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
-#ifndef CONFIG_FSL_DDR2
+#ifndef CONFIG_SYS_FSL_DDR2
msize = spd_sdram() * 1024 * 1024;
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
ddr_enable_ecc(msize);
*/
sdram_init();
- /* return total bus SDRAM size(bytes) -- DDR */
- return msize;
+ /* set total bus SDRAM size(bytes) -- DDR */
+ gd->ram_size = msize;
+
+ return 0;
}
#if !defined(CONFIG_SPD_EEPROM)
int fixed_sdram(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 msize = 0;
- u32 ddr_size;
- u32 ddr_size_log2;
-
- msize = CONFIG_SYS_DDR_SIZE;
- for (ddr_size = msize << 20, ddr_size_log2 = 0;
- (ddr_size > 1);
- ddr_size = ddr_size>>1, ddr_size_log2++) {
- if (ddr_size & 1) {
- return -1;
- }
- }
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+ u32 msize = CONFIG_SYS_DDR_SIZE;
+ u32 ddr_size = msize << 20; /* DDR size in bytes */
+ u32 ddr_size_log2 = __ilog2(ddr_size);
+
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CONFIG_SYS_DDR_SIZE != 256)
im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
#else
- im->ddr.csbnds[2].csbnds = 0x0000000f;
- im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG;
+
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+ im->ddr.csbnds[2].csbnds =
+ ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
+ CSBNDS_EA_SHIFT) & CSBNDS_EA);
+ im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
/* currently we use only one CS, so disable the other banks */
im->ddr.cs_config[0] = 0;
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile fsl_lbc_t *lbc = &immap->im_lbc;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
-
+ const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
+ LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
+ LSDMR_WRC3 | LSDMR_CL3;
/*
* Setup SDRAM Base and Option Registers, already done in cpu_init.c
*/
/* setup mtrpt, lsrt and lbcr for LB bus */
- lbc->lbcr = CONFIG_SYS_LBC_LBCR;
- lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
- lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+ lbc->lbcr = 0x00000000;
+ /* LB refresh timer prescal, 266MHz/32 */
+ lbc->mrtpr = 0x20000000;
+ /* LB sdram refresh timer, about 6us */
+ lbc->lsrt = 0x32000000;
asm("sync");
/*
* Configure the SDRAM controller Machine Mode Register.
*/
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
+ /* 0x40636733; normal operation */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
+
+ /* 0x68636733; precharge all the banks */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
+ /* 0x48636733; auto refresh */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
asm("sync");
/*1 times*/
*sdram_addr = 0xff;
udelay(100);
/* 0x58636733; mode register write operation */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
+ /* 0x40636733; normal operation */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
iopd->dat |= SPI_CS_MASK;
}
-#endif /* CONFIG_HARD_SPI */
+#endif
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, struct bd_info *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
+
+ return 0;
}
#endif
projects / platform / kernel / u-boot.git / blobdiff