Merge branch 'next' of git://git.denx.de/u-boot-avr32

[platform/kernel/u-boot.git] / board / freescale / m5253evbe / m5253evbe.c

diff --git a/board/freescale/m5253evbe/m5253evbe.c b/board/freescale/m5253evbe/m5253evbe.c
index 43aa84d..f3b1efd 100644 (file)
--- a/board/freescale/m5253evbe/m5253evbe.c
+++ b/board/freescale/m5253evbe/m5253evbe.c
@@ -34,10 +34,8 @@ int checkboard(void)
        return 0;
 };
 
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
 {
-       int i;
-
        /*
         * Check to see if the SDRAM has already been initialized
         * by a run control tool
@@ -50,21 +48,27 @@ long int initdram(int board_type)
 
                /* Initialize DRAM Control Register: DCR */
                mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
+               asm("nop");
 
-               mbar_writeLong(MCFSIM_DACR0, 0x00003224);
+               mbar_writeLong(MCFSIM_DACR0, 0x00002320);
+               asm("nop");
 
                /* Initialize DMR0 */
                dramsize = ((CFG_SDRAM_SIZE << 20) - 1) & 0xFFFC0000;
                mbar_writeLong(MCFSIM_DMR0, dramsize | 1);
+               asm("nop");
 
-               mbar_writeLong(MCFSIM_DACR0, 0x0000322c);
+               mbar_writeLong(MCFSIM_DACR0, 0x00002328);
+               asm("nop");
 
                /* Write to this block to initiate precharge */
                *(u32 *) (CFG_SDRAM_BASE) = 0xa5a5a5a5;
+               asm("nop");
 
                /* Set RE bit in DACR */
                mbar_writeLong(MCFSIM_DACR0,
                               mbar_readLong(MCFSIM_DACR0) | 0x8000);
+               asm("nop");
 
                /* Wait for at least 8 auto refresh cycles to occur */
                udelay(500);
@@ -72,6 +76,7 @@ long int initdram(int board_type)
                /* Finish the configuration by issuing the MRS */
                mbar_writeLong(MCFSIM_DACR0,
                               mbar_readLong(MCFSIM_DACR0) | 0x0040);
+               asm("nop");
 
                *(u32 *) (CFG_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
        }