Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spi

[platform/kernel/u-boot.git] / board / freescale / ls2080ardb / eth_ls2080rdb.c

diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c
index ba584c8..f0f6ca5 100644 (file)
--- a/board/freescale/ls2080ardb/eth_ls2080rdb.c
+++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c
@@ -1,12 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2015 Freescale Semiconductor, Inc.
  *
- *
- * SPDX-License-Identifier:     GPL-2.0+
  */
 
 #include <common.h>
 #include <command.h>
+#include <net.h>
 #include <netdev.h>
 #include <malloc.h>
 #include <fsl_mdio.h>
@@ -16,15 +16,15 @@
 #include <asm/io.h>
 #include <exports.h>
 #include <asm/arch/fsl_serdes.h>
+#include <fsl-mc/fsl_mc.h>
 #include <fsl-mc/ldpaa_wriop.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define MC_BOOT_ENV_VAR "mcinitcmd"
 int board_eth_init(bd_t *bis)
 {
+#ifndef CONFIG_DM_ETH
 #if defined(CONFIG_FSL_MC_ENET)
-       char *mc_boot_env_var;
        int i, interface;
        struct memac_mdio_info mdio_info;
        struct mii_dev *dev;
@@ -52,21 +52,21 @@ int board_eth_init(bd_t *bis)
 
        switch (srds_s1) {
        case 0x2A:
-               wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
-               wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
-               wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
-               wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
-               wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1);
-               wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2);
-               wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
-               wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
+               wriop_set_phy_address(WRIOP1_DPMAC1, 0, CORTINA_PHY_ADDR1);
+               wriop_set_phy_address(WRIOP1_DPMAC2, 0, CORTINA_PHY_ADDR2);
+               wriop_set_phy_address(WRIOP1_DPMAC3, 0, CORTINA_PHY_ADDR3);
+               wriop_set_phy_address(WRIOP1_DPMAC4, 0, CORTINA_PHY_ADDR4);
+               wriop_set_phy_address(WRIOP1_DPMAC5, 0, AQ_PHY_ADDR1);
+               wriop_set_phy_address(WRIOP1_DPMAC6, 0, AQ_PHY_ADDR2);
+               wriop_set_phy_address(WRIOP1_DPMAC7, 0, AQ_PHY_ADDR3);
+               wriop_set_phy_address(WRIOP1_DPMAC8, 0, AQ_PHY_ADDR4);
 
                break;
        case 0x4B:
-               wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
-               wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
-               wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
-               wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
+               wriop_set_phy_address(WRIOP1_DPMAC1, 0, CORTINA_PHY_ADDR1);
+               wriop_set_phy_address(WRIOP1_DPMAC2, 0, CORTINA_PHY_ADDR2);
+               wriop_set_phy_address(WRIOP1_DPMAC3, 0, CORTINA_PHY_ADDR3);
+               wriop_set_phy_address(WRIOP1_DPMAC4, 0, CORTINA_PHY_ADDR4);
 
                break;
        default:
@@ -98,11 +98,9 @@ int board_eth_init(bd_t *bis)
                }
        }
 
-       mc_boot_env_var = getenv(MC_BOOT_ENV_VAR);
-       if (mc_boot_env_var)
-               run_command_list(mc_boot_env_var, -1, 0);
        cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
+#endif /* CONFIG_FSL_MC_ENET */
+#endif /* !CONFIG_DM_ETH */
 
 #ifdef CONFIG_PHY_AQUANTIA
        /*
@@ -116,5 +114,17 @@ int board_eth_init(bd_t *bis)
        gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
        gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
 #endif
+
+#ifdef CONFIG_DM_ETH
+       return 0;
+#else
        return pci_eth_init(bis);
+#endif
+}
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+       mc_env_boot();
 }
+#endif /* CONFIG_RESET_PHY_R */