+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor, Inc.
*
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
+#include <net.h>
#include <netdev.h>
#include <malloc.h>
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
#include <fm_eth.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <exports.h>
#include <asm/arch/fsl_serdes.h>
+#include <fsl-mc/fsl_mc.h>
#include <fsl-mc/ldpaa_wriop.h>
DECLARE_GLOBAL_DATA_PTR;
-int board_eth_init(bd_t *bis)
+int board_eth_init(struct bd_info *bis)
{
+#ifndef CONFIG_DM_ETH
#if defined(CONFIG_FSL_MC_ENET)
int i, interface;
struct memac_mdio_info mdio_info;
struct mii_dev *dev;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 srds_s1;
struct memac_mdio_controller *reg;
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
- reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO1;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the EMI 1 */
fm_memac_mdio_init(bis, &mdio_info);
- reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO2;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
switch (srds_s1) {
case 0x2A:
- wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
- wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
- wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
- wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
- wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1);
- wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2);
- wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
- wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
+ wriop_set_phy_address(WRIOP1_DPMAC1, 0, CORTINA_PHY_ADDR1);
+ wriop_set_phy_address(WRIOP1_DPMAC2, 0, CORTINA_PHY_ADDR2);
+ wriop_set_phy_address(WRIOP1_DPMAC3, 0, CORTINA_PHY_ADDR3);
+ wriop_set_phy_address(WRIOP1_DPMAC4, 0, CORTINA_PHY_ADDR4);
+ wriop_set_phy_address(WRIOP1_DPMAC5, 0, AQ_PHY_ADDR1);
+ wriop_set_phy_address(WRIOP1_DPMAC6, 0, AQ_PHY_ADDR2);
+ wriop_set_phy_address(WRIOP1_DPMAC7, 0, AQ_PHY_ADDR3);
+ wriop_set_phy_address(WRIOP1_DPMAC8, 0, AQ_PHY_ADDR4);
+
+ break;
+ case 0x4B:
+ wriop_set_phy_address(WRIOP1_DPMAC1, 0, CORTINA_PHY_ADDR1);
+ wriop_set_phy_address(WRIOP1_DPMAC2, 0, CORTINA_PHY_ADDR2);
+ wriop_set_phy_address(WRIOP1_DPMAC3, 0, CORTINA_PHY_ADDR3);
+ wriop_set_phy_address(WRIOP1_DPMAC4, 0, CORTINA_PHY_ADDR4);
break;
default:
}
cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
+#endif /* CONFIG_FSL_MC_ENET */
+#endif /* !CONFIG_DM_ETH */
#ifdef CONFIG_PHY_AQUANTIA
/*
gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
#endif
+
+#ifdef CONFIG_DM_ETH
+ return 0;
+#else
return pci_eth_init(bis);
+#endif
+}
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+ mc_env_boot();
}
+#endif /* CONFIG_RESET_PHY_R */