Merge branch 'master' of git://git.denx.de/u-boot-samsung

[platform/kernel/u-boot.git] / board / freescale / ls2080ardb / ddr.c

diff --git a/board/freescale/ls2080ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c
index ae681de..01f7d82 100644 (file)
--- a/board/freescale/ls2080ardb/ddr.c
+++ b/board/freescale/ls2080ardb/ddr.c
@@ -7,6 +7,8 @@
 #include <common.h>
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr_dimm_params.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/clock.h>
 #include "ddr.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -133,11 +135,22 @@ found:
        /* Enable ZQ calibration */
        popts->zq_en = 1;
 
+       /* optimize cpo for erratum A-009942 */
+       popts->cpo_sample = 0x6e;
+
        if (ddr_freq < 2350) {
-               popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
-                                 DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
-               popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
-                                 DDR_CDR2_VREF_RANGE_2;
+               if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) {
+                       /* four chip-selects */
+                       popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+                                         DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+                       popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm);
+                       popts->twot_en = 1;     /* enable 2T timing */
+               } else {
+                       popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+                                         DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
+                       popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
+                                         DDR_CDR2_VREF_RANGE_2;
+               }
        } else {
                popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
                                  DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
@@ -146,54 +159,15 @@ found:
        }
 }
 
-phys_size_t initdram(int board_type)
+int fsl_initdram(void)
 {
-       phys_size_t dram_size;
-
 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-       return fsl_ddr_sdram_size();
+       gd->ram_size = fsl_ddr_sdram_size();
 #else
        puts("Initializing DDR....using SPD\n");
 
-       dram_size = fsl_ddr_sdram();
-#endif
-
-       return dram_size;
-}
-
-void dram_init_banksize(void)
-{
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
-       phys_size_t dp_ddr_size;
+       gd->ram_size = fsl_ddr_sdram();
 #endif
 
-       gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-       if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
-               gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
-               gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
-               gd->bd->bi_dram[1].size = gd->ram_size -
-                                         CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
-       } else {
-               gd->bd->bi_dram[0].size = gd->ram_size;
-       }
-
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
-       /* initialize DP-DDR here */
-       puts("DP-DDR:  ");
-       /*
-        * DDR controller use 0 as the base address for binding.
-        * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
-        */
-       dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
-                                         CONFIG_DP_DDR_CTRL,
-                                         CONFIG_DP_DDR_NUM_CTRLS,
-                                         CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
-                                         NULL, NULL, NULL);
-       if (dp_ddr_size) {
-               gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
-               gd->bd->bi_dram[2].size = dp_ddr_size;
-       } else {
-               puts("Not detected");
-       }
-#endif
+       return 0;
 }