// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2022 NXP
*/
#include <common.h>
+#include <clock_legacy.h>
+#include <display_options.h>
#include <env.h>
#include <i2c.h>
#include <init.h>
#include <netdev.h>
#include <fsl_ifc.h>
#include <fsl_ddr.h>
-#include <fsl_sec.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <fdt_support.h>
},
{
"nand",
- CONFIG_SYS_NAND_CSPR,
- CONFIG_SYS_NAND_CSPR_EXT,
- CONFIG_SYS_NAND_AMASK,
- CONFIG_SYS_NAND_CSOR,
+ CFG_SYS_NAND_CSPR,
+ CFG_SYS_NAND_CSPR_EXT,
+ CFG_SYS_NAND_AMASK,
+ CFG_SYS_NAND_CSOR,
{
- CONFIG_SYS_NAND_FTIM0,
- CONFIG_SYS_NAND_FTIM1,
- CONFIG_SYS_NAND_FTIM2,
- CONFIG_SYS_NAND_FTIM3
+ CFG_SYS_NAND_FTIM0,
+ CFG_SYS_NAND_FTIM1,
+ CFG_SYS_NAND_FTIM2,
+ CFG_SYS_NAND_FTIM3
},
},
{
struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"nand",
- CONFIG_SYS_NAND_CSPR,
- CONFIG_SYS_NAND_CSPR_EXT,
- CONFIG_SYS_NAND_AMASK,
- CONFIG_SYS_NAND_CSOR,
+ CFG_SYS_NAND_CSPR,
+ CFG_SYS_NAND_CSPR_EXT,
+ CFG_SYS_NAND_AMASK,
+ CFG_SYS_NAND_CSOR,
{
- CONFIG_SYS_NAND_FTIM0,
- CONFIG_SYS_NAND_FTIM1,
- CONFIG_SYS_NAND_FTIM2,
- CONFIG_SYS_NAND_FTIM3
+ CFG_SYS_NAND_FTIM0,
+ CFG_SYS_NAND_FTIM1,
+ CFG_SYS_NAND_FTIM2,
+ CFG_SYS_NAND_FTIM3
},
},
{
#endif
}
+#ifdef CONFIG_DYNAMIC_SYS_CLK_FREQ
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
return 66666666;
}
+#endif
+#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
unsigned long get_board_ddr_clk(void)
{
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
return 66666666;
}
+#endif
#if !defined(CONFIG_SPL_BUILD)
void board_retimer_init(void)
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
}
if (disable_ifc) {
- offset = fdt_path_offset(fdt, "/soc/ifc/nor");
+ offset = fdt_path_offset(fdt, "/soc/memory-controller/nor");
if (offset < 0)
- offset = fdt_path_offset(fdt, "/ifc/nor");
+ offset = fdt_path_offset(fdt, "/memory-controller/nor");
} else {
offset = fdt_path_offset(fdt, "/soc/quadspi");
#else
#ifdef CONFIG_FSL_QSPI
- offset = fdt_path_offset(fdt, "/soc/ifc/nor");
+ offset = fdt_path_offset(fdt, "/soc/memory-controller/nor");
if (offset < 0)
- offset = fdt_path_offset(fdt, "/ifc/nor");
+ offset = fdt_path_offset(fdt, "/memory-controller/nor");
#else
offset = fdt_path_offset(fdt, "/soc/quadspi");
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
void *env_sf_get_env_addr(void)
{
- return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
+ return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
}
#endif
#endif