// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2022 NXP
*/
#include <common.h>
+#include <clock_legacy.h>
#include <env.h>
#include <i2c.h>
#include <init.h>
#include <netdev.h>
#include <fsl_ifc.h>
#include <fsl_ddr.h>
-#include <fsl_sec.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <fdt_support.h>
#endif
}
+#ifdef CONFIG_DYNAMIC_SYS_CLK_FREQ
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
return 66666666;
}
+#endif
+#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
unsigned long get_board_ddr_clk(void)
{
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
return 66666666;
}
+#endif
#if !defined(CONFIG_SPL_BUILD)
void board_retimer_init(void)
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
board_retimer_init();
-#ifdef CONFIG_ENV_IS_NOWHERE
- gd->env_addr = (ulong)&default_environment[0];
-#endif
-
#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
/* invert AQR105 IRQ pins polarity */
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
}
if (disable_ifc) {
- offset = fdt_path_offset(fdt, "/soc/ifc/nor");
+ offset = fdt_path_offset(fdt, "/soc/memory-controller/nor");
if (offset < 0)
- offset = fdt_path_offset(fdt, "/ifc/nor");
+ offset = fdt_path_offset(fdt, "/memory-controller/nor");
} else {
offset = fdt_path_offset(fdt, "/soc/quadspi");
#else
#ifdef CONFIG_FSL_QSPI
- offset = fdt_path_offset(fdt, "/soc/ifc/nor");
+ offset = fdt_path_offset(fdt, "/soc/memory-controller/nor");
if (offset < 0)
- offset = fdt_path_offset(fdt, "/ifc/nor");
+ offset = fdt_path_offset(fdt, "/memory-controller/nor");
#else
offset = fdt_path_offset(fdt, "/soc/quadspi");