global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace

[platform/kernel/u-boot.git] / board / freescale / ls1043ardb / ls1043ardb.c

diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index 9bc78d6..799900e 100644 (file)
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -1,10 +1,13 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2021-2022 NXP
  */
 
 #include <common.h>
 #include <i2c.h>
+#include <init.h>
+#include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
@@ -18,7 +21,6 @@
 #include <fm_eth.h>
 #include <fsl_esdhc.h>
 #include <fsl_ifc.h>
-#include <fsl_sec.h>
 #include "cpld.h"
 #ifdef CONFIG_U_QE
 #include <fsl_qe.h>
@@ -165,7 +167,7 @@ int checkboard(void)
 
        if (cfg_rcw_src == 0x25)
                printf("vBank %d\n", CPLD_READ(vbank));
-       else if (cfg_rcw_src == 0x106)
+       else if ((cfg_rcw_src == 0x106) || (cfg_rcw_src == 0x118))
                puts("NAND\n");
        else
                printf("Invalid setting of SW4\n");
@@ -186,7 +188,7 @@ int checkboard(void)
 
 int board_init(void)
 {
-       struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+       struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
        erratum_a010315();
@@ -209,14 +211,14 @@ int board_init(void)
        out_le32(SMMU_NSCR0, val);
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-       sec_init();
-#endif
-
 #ifdef CONFIG_FSL_LS_PPA
        ppa_init();
 #endif
 
+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
+       pci_init();
+#endif
+
 #ifdef CONFIG_U_QE
        u_qe_init();
 #endif
@@ -228,7 +230,7 @@ int board_init(void)
 
 int config_board_mux(void)
 {
-       struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+       struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
        u32 usb_pwrfault;
 
        if (hwconfig("qe-hdlc")) {
@@ -270,7 +272,40 @@ void fdt_del_qe(void *blob)
        }
 }
 
-int ft_board_setup(void *blob, bd_t *bd)
+/* Update the address of the Aquantia PHY on the MDIO bus for boards revision
+ * v7.0 and up. Also rename the PHY node to align with the address change.
+ */
+void fdt_fixup_phy_addr(void *blob)
+{
+       const char phy_path[] =
+               "/soc/fman@1a00000/mdio@fd000/ethernet-phy@1";
+       int ret, offset, new_addr = AQR113C_PHY_ADDR;
+       char new_name[] = "ethernet-phy@00";
+
+       if (CPLD_READ(pcba_ver) < 0x7)
+               return;
+
+       offset = fdt_path_offset(blob, phy_path);
+       if (offset < 0) {
+               printf("ethernet-phy@1 node not found in the dts\n");
+               return;
+       }
+
+       ret = fdt_setprop_u32(blob, offset, "reg", new_addr);
+       if (ret < 0) {
+               printf("Unable to set 'reg' for node ethernet-phy@1: %s\n",
+                      fdt_strerror(ret));
+               return;
+       }
+
+       sprintf(new_name, "ethernet-phy@%x", new_addr);
+       ret = fdt_set_name(blob, offset, new_name);
+       if (ret < 0)
+               printf("Unable to rename node ethernet-phy@1: %s\n",
+                      fdt_strerror(ret));
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
 {
        u64 base[CONFIG_NR_DRAM_BANKS];
        u64 size[CONFIG_NR_DRAM_BANKS];
@@ -285,8 +320,11 @@ int ft_board_setup(void *blob, bd_t *bd)
        ft_cpu_setup(blob, bd);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
+#ifndef CONFIG_DM_ETH
        fdt_fixup_fman_ethernet(blob);
 #endif
+       fdt_fixup_phy_addr(blob);
+#endif
 
        fdt_fixup_icid(blob);
 
@@ -309,6 +347,58 @@ int ft_board_setup(void *blob, bd_t *bd)
        return 0;
 }
 
+void nand_fixup(void)
+{
+       u32 csor = 0;
+
+       if (CPLD_READ(pcba_ver) < 0x7)
+               return;
+
+    /* Change NAND Flash PGS/SPRZ configuration */
+       csor = CONFIG_SYS_NAND_CSOR;
+       if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K)
+               csor = (csor & ~(CSOR_NAND_PGS_MASK)) | CSOR_NAND_PGS_4K;
+
+       if ((csor & CSOR_NAND_SPRZ_MASK) == CSOR_NAND_SPRZ_64)
+               csor = (csor & ~(CSOR_NAND_SPRZ_MASK)) | CSOR_NAND_SPRZ_224;
+
+       if (IS_ENABLED(CONFIG_TFABOOT)) {
+               u8 cfg_rcw_src1, cfg_rcw_src2;
+               u16 cfg_rcw_src;
+
+               cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
+               cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
+               cpld_rev_bit(&cfg_rcw_src1);
+               cfg_rcw_src = cfg_rcw_src1;
+               cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
+
+               if (cfg_rcw_src == 0x25)
+                       set_ifc_csor(IFC_CS1, csor);
+               else if (cfg_rcw_src == 0x118)
+                       set_ifc_csor(IFC_CS0, csor);
+               else
+                       printf("Invalid setting\n");
+       } else {
+               if (IS_ENABLED(CONFIG_NAND_BOOT))
+                       set_ifc_csor(IFC_CS0, csor);
+               else
+                       set_ifc_csor(IFC_CS1, csor);
+       }
+}
+
+#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
+int board_fix_fdt(void *blob)
+{
+       /* nand driver fix up */
+       nand_fixup();
+
+       /* fdt fix up */
+       fdt_fixup_phy_addr(blob);
+
+       return 0;
+}
+#endif
+
 u8 flash_read8(void *addr)
 {
        return __raw_readb(addr + 1);