// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor, Inc.
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
*/
#include <common.h>
+#include <clock_legacy.h>
#include <i2c.h>
#include <fdt_support.h>
#include <fsl_ddr_sdram.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
#include <spl.h>
+#include "../common/i2c_mux.h"
#include "../common/qixis.h"
#include "ls1043aqds_qixis.h"
return 66666666;
}
-int select_i2c_ch_pca9547(u8 ch, int bus_num)
-{
- int ret;
-
-#ifdef CONFIG_DM_I2C
- struct udevice *dev;
-
- ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
- 1, &dev);
- if (ret) {
- printf("%s: Cannot find udev for a bus %d\n", __func__,
- bus_num);
- return ret;
- }
- ret = dm_i2c_write(dev, 0, &ch, 1);
-#else
- ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
-#endif
- if (ret) {
- puts("PCA: failed to select proper channel\n");
- return ret;
- }
-
- return 0;
-}
-
int dram_init(void)
{
/*
/* Retimer is connected to I2C1_CH7_CH5 */
select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num);
reg = I2C_MUX_CH5;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
int ret;
int board_early_init_f(void)
{
+ u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR;
#ifdef CONFIG_HAS_FSL_XHCI_USB
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
u32 usb_pwrfault;
#endif
#ifdef CONFIG_LPUART
u8 uart;
#endif
-#ifdef CONFIG_SYS_I2C
-#ifdef CONFIG_SYS_I2C_EARLY_INIT
+ /*
+ * Enable secure system counter for timer
+ */
+ out_le32(cntcr, 0x1);
+
+#if defined(CONFIG_SYS_I2C_EARLY_INIT)
i2c_early_init_f();
#endif
-#endif
fsl_lsch2_early_init_f();
#ifdef CONFIG_HAS_FSL_XHCI_USB
bool is_warm_boot(void)
{
#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
return 1;
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
board_retimer_init();
-#ifdef CONFIG_SYS_FSL_SERDES
+#ifdef CFG_SYS_FSL_SERDES
config_serdes_mux();
#endif
}
#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, struct bd_info *bd)
{
u64 base[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
fdt_fixup_memory_banks(blob, base, size, 2);
ft_cpu_setup(blob, bd);
-#ifdef CONFIG_SYS_DPAA_FMAN
- fdt_fixup_fman_ethernet(blob);
+#ifdef CONFIG_FMAN_ENET
fdt_fixup_board_enet(blob);
#endif
#if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
void *env_sf_get_env_addr(void)
{
- return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
+ return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
}
#endif