Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spi

[platform/kernel/u-boot.git] / board / freescale / ls1028a / ls1028a.c

diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c
index e5de4eb..1e2973f 100644 (file)
--- a/board/freescale/ls1028a/ls1028a.c
+++ b/board/freescale/ls1028a/ls1028a.c
@@ -11,8 +11,9 @@
 #include <hwconfig.h>
 #include <fdt_support.h>
 #include <linux/libfdt.h>
-#include <environment.h>
+#include <env_internal.h>
 #include <asm/arch-fsl-layerscape/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
 #include <i2c.h>
 #include <asm/arch/soc.h>
 #ifdef CONFIG_FSL_LS_PPA
@@ -24,11 +25,13 @@
 #include <fdtdec.h>
 #include <miiphy.h>
 #include "../common/qixis.h"
+#include "../drivers/net/fsl_enetc.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
 int config_board_mux(void)
 {
+#ifndef CONFIG_LPUART
 #if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
        u8 reg;
 
@@ -53,15 +56,28 @@ int config_board_mux(void)
        reg &= ~(0xc0);
        QIXIS_WRITE(brdcfg[15], reg);
 #endif
+#endif
+
        return 0;
 }
 
+#ifdef CONFIG_LPUART
+u32 get_lpuart_clk(void)
+{
+       return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV;
+}
+#endif
+
 int board_init(void)
 {
 #ifdef CONFIG_ENV_IS_NOWHERE
        gd->env_addr = (ulong)&default_environment[0];
 #endif
 
+#ifdef CONFIG_FSL_CAAM
+       sec_init();
+#endif
+
 #ifdef CONFIG_FSL_LS_PPA
        ppa_init();
 #endif
@@ -73,7 +89,27 @@ int board_init(void)
 #if defined(CONFIG_TARGET_LS1028ARDB)
        u8 val = I2C_MUX_CH_DEFAULT;
 
+#ifndef CONFIG_DM_I2C
        i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
+#else
+       struct udevice *dev;
+
+       if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev))
+               dm_i2c_write(dev, 0x0b, &val, 1);
+#endif
+#endif
+
+#if defined(CONFIG_TARGET_LS1028ARDB)
+       u8 reg;
+
+       reg = QIXIS_READ(brdcfg[4]);
+       /*
+        * Field | Function
+        * 3     | DisplayPort Power Enable (net DP_PWR_EN):
+        * DPPWR | 0= DP_PWR is enabled.
+        */
+       reg &= ~(DP_PWD_EN_DEFAULT_MASK);
+       QIXIS_WRITE(brdcfg[4], reg);
 #endif
        return 0;
 }
@@ -83,8 +119,8 @@ int board_eth_init(bd_t *bis)
        return pci_eth_init(bis);
 }
 
-#if defined(CONFIG_ARCH_MISC_INIT)
-int arch_misc_init(void)
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
 {
        config_board_mux();
 
@@ -94,11 +130,33 @@ int arch_misc_init(void)
 
 int board_early_init_f(void)
 {
+#ifdef CONFIG_LPUART
+       u8 uart;
+#endif
+
 #ifdef CONFIG_SYS_I2C_EARLY_INIT
        i2c_early_init_f();
 #endif
 
        fsl_lsch3_early_init_f();
+
+#ifdef CONFIG_LPUART
+       /*
+        * Field| Function
+        * --------------------------------------------------------------
+        * 7-6  | Controls I2C3 routing (net CFG_MUX_I2C3):
+        * I2C3 | 11= Routes {SCL, SDA} to LPUART1 header as {SOUT, SIN}.
+        * --------------------------------------------------------------
+        * 5-4  | Controls I2C4 routing (net CFG_MUX_I2C4):
+        * I2C4 |11= Routes {SCL, SDA} to LPUART1 header as {CTS_B, RTS_B}.
+        */
+       /* use lpuart0 as system console */
+       uart = QIXIS_READ(brdcfg[13]);
+       uart &= ~CFG_LPUART_MUX_MASK;
+       uart |= CFG_LPUART_EN;
+       QIXIS_WRITE(brdcfg[13], uart);
+#endif
+
        return 0;
 }
 
@@ -109,6 +167,46 @@ void detail_board_ddr_info(void)
        print_ddr_info(0);
 }
 
+int esdhc_status_fixup(void *blob, const char *compat)
+{
+       void __iomem *dcfg_ccsr = (void __iomem *)DCFG_BASE;
+       char esdhc1_path[] = "/soc/mmc@2140000";
+       char esdhc2_path[] = "/soc/mmc@2150000";
+       char dspi1_path[] = "/soc/spi@2100000";
+       char dspi2_path[] = "/soc/spi@2110000";
+       u32 mux_sdhc1, mux_sdhc2;
+       u32 io = 0;
+
+       /*
+        * The PMUX IO-expander for mux select is used to control
+        * the muxing of various onboard interfaces.
+        */
+
+       io = in_le32(dcfg_ccsr + DCFG_RCWSR12);
+       mux_sdhc1 = (io >> DCFG_RCWSR12_SDHC_SHIFT) & DCFG_RCWSR12_SDHC_MASK;
+
+       /* Disable esdhc1/dspi1 if not selected. */
+       if (mux_sdhc1 != 0)
+               do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
+                                sizeof("disabled"), 1);
+       if (mux_sdhc1 != 2)
+               do_fixup_by_path(blob, dspi1_path, "status", "disabled",
+                                sizeof("disabled"), 1);
+
+       io = in_le32(dcfg_ccsr + DCFG_RCWSR13);
+       mux_sdhc2 = (io >> DCFG_RCWSR13_SDHC_SHIFT) & DCFG_RCWSR13_SDHC_MASK;
+
+       /* Disable esdhc2/dspi2 if not selected. */
+       if (mux_sdhc2 != 0)
+               do_fixup_by_path(blob, esdhc2_path, "status", "disabled",
+                                sizeof("disabled"), 1);
+       if (mux_sdhc2 != 2)
+               do_fixup_by_path(blob, dspi2_path, "status", "disabled",
+                                sizeof("disabled"), 1);
+
+       return 0;
+}
+
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
@@ -135,6 +233,12 @@ int ft_board_setup(void *blob, bd_t *bd)
 
        fdt_fixup_memory_banks(blob, base, size, 2);
 
+       fdt_fixup_icid(blob);
+
+#ifdef CONFIG_FSL_ENETC
+       fdt_fixup_enetc_mac(blob);
+#endif
+
        return 0;
 }
 #endif