command: Remove the cmd_tbl_t typedef

[platform/kernel/u-boot.git] / board / freescale / ls1021atwr / ls1021atwr.c

diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index 863bf76..c7f7baa 100644 (file)
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -1,21 +1,25 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
  */
 
 #include <common.h>
+#include <clock_legacy.h>
+#include <command.h>
+#include <fdt_support.h>
 #include <i2c.h>
+#include <init.h>
+#include <net.h>
 #include <asm/io.h>
 #include <asm/arch/immap_ls102xa.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/ls102xa_devdis.h>
 #include <asm/arch/ls102xa_soc.h>
-#include <asm/arch/ls102xa_sata.h>
 #include <hwconfig.h>
 #include <mmc.h>
 #include <fsl_csu.h>
-#include <fsl_esdhc.h>
 #include <fsl_ifc.h>
 #include <fsl_immap.h>
 #include <netdev.h>
@@ -223,6 +227,8 @@ int dram_init(void)
        ddrmc_init();
 #endif
 
+       erratum_a008850_post();
+
        gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 
 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
@@ -232,59 +238,8 @@ int dram_init(void)
        return 0;
 }
 
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg esdhc_cfg[1] = {
-       {CONFIG_SYS_FSL_ESDHC_ADDR},
-};
-
-int board_mmc_init(bd_t *bis)
-{
-       esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-
-       return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
-}
-#endif
-
 int board_eth_init(bd_t *bis)
 {
-#ifdef CONFIG_TSEC_ENET
-       struct fsl_pq_mdio_info mdio_info;
-       struct tsec_info_struct tsec_info[4];
-       int num = 0;
-
-#ifdef CONFIG_TSEC1
-       SET_STD_TSEC_INFO(tsec_info[num], 1);
-       if (is_serdes_configured(SGMII_TSEC1)) {
-               puts("eTSEC1 is in sgmii mode.\n");
-               tsec_info[num].flags |= TSEC_SGMII;
-       }
-       num++;
-#endif
-#ifdef CONFIG_TSEC2
-       SET_STD_TSEC_INFO(tsec_info[num], 2);
-       if (is_serdes_configured(SGMII_TSEC2)) {
-               puts("eTSEC2 is in sgmii mode.\n");
-               tsec_info[num].flags |= TSEC_SGMII;
-       }
-       num++;
-#endif
-#ifdef CONFIG_TSEC3
-       SET_STD_TSEC_INFO(tsec_info[num], 3);
-       tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
-       num++;
-#endif
-       if (!num) {
-               printf("No TSECs initialized\n");
-               return 0;
-       }
-
-       mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
-       mdio_info.name = DEFAULT_MII_NAME;
-       fsl_pq_mdio_init(bis, &mdio_info);
-
-       tsec_eth_init(bis, tsec_info, num);
-#endif
-
        return pci_eth_init(bis);
 }
 
@@ -468,6 +423,7 @@ void board_init_f(ulong dummy)
 
        preloader_console_init();
 
+       timer_init();
        dram_init();
 
        /* Allow OCRAM access permission as R/W */
@@ -494,14 +450,37 @@ void board_init_f(ulong dummy)
 /* program the regulator (MC34VR500) to support deep sleep */
 void ls1twr_program_regulator(void)
 {
-       unsigned int i2c_bus;
        u8 i2c_device_id;
 
 #define LS1TWR_I2C_BUS_MC34VR500       1
 #define MC34VR500_ADDR                 0x8
 #define MC34VR500_DEVICEID             0x4
 #define MC34VR500_DEVICEID_MASK                0x0f
+#ifdef CONFIG_DM_I2C
+       struct udevice *dev;
+       int ret;
+
+       ret = i2c_get_chip_for_busnum(LS1TWR_I2C_BUS_MC34VR500, MC34VR500_ADDR,
+                                     1, &dev);
+       if (ret) {
+               printf("%s: Cannot find udev for a bus %d\n", __func__,
+                      LS1TWR_I2C_BUS_MC34VR500);
+               return;
+       }
+       i2c_device_id = dm_i2c_reg_read(dev, 0x0) &
+                                       MC34VR500_DEVICEID_MASK;
+       if (i2c_device_id != MC34VR500_DEVICEID) {
+               printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
+               return;
+       }
 
+       dm_i2c_reg_write(dev, 0x31, 0x4);
+       dm_i2c_reg_write(dev, 0x4d, 0x4);
+       dm_i2c_reg_write(dev, 0x6d, 0x38);
+       dm_i2c_reg_write(dev, 0x6f, 0x37);
+       dm_i2c_reg_write(dev, 0x71, 0x30);
+#else
+       unsigned int i2c_bus;
        i2c_bus = i2c_get_bus_num();
        i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
        i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
@@ -518,6 +497,7 @@ void ls1twr_program_regulator(void)
        i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
 
        i2c_set_bus_num(i2c_bus);
+#endif
 }
 #endif
 
@@ -556,9 +536,6 @@ void spl_board_init(void)
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
-#ifdef CONFIG_SCSI_AHCI_PLAT
-       ls1021a_sata_init();
-#endif
 #ifdef CONFIG_CHAIN_OF_TRUST
        fsl_setenv_chain_of_trust();
 #endif
@@ -636,8 +613,8 @@ static void convert_flash_bank(char bank)
        cpld_data->system_rst = CONFIG_RESET;
 }
 
-static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
-                         char * const argv[])
+static int flash_bank_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
+                         char *const argv[])
 {
        if (argc != 2)
                return CMD_RET_USAGE;
@@ -657,8 +634,8 @@ U_BOOT_CMD(
        "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
 );
 
-static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
-                         char * const argv[])
+static int cpld_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
+                         char *const argv[])
 {
        struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 
@@ -716,8 +693,8 @@ static void print_serdes_mux(void)
                printf("B.\n");
 }
 
-static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
-                         char * const argv[])
+static int serdes_mux_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
+                         char *const argv[])
 {
        if (argc != 2)
                return CMD_RET_USAGE;