layerscape: Disable CONFIG_FMAN_ENET on *aqds* platforms
[platform/kernel/u-boot.git] / board / freescale / ls1012ardb / eth.c
index 8e6cd0a..565f800 100644 (file)
@@ -1,12 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2015-2016 Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
- *
- * SPDX-License-Identifier:GPL-2.0+
  */
 
 #include <common.h>
 #include <dm.h>
+#include <net.h>
 #include <asm/io.h>
 #include <netdev.h>
 #include <fm_eth.h>
@@ -18,6 +18,7 @@
 #include <asm/arch-fsl-layerscape/config.h>
 #include <asm/arch-fsl-layerscape/immap_lsch2.h>
 #include <asm/arch/fsl_serdes.h>
+#include <linux/delay.h>
 #include <net/pfe_eth/pfe_eth.h>
 #include <dm/platform_data/pfe_dm_eth.h>
 #include <i2c.h>
@@ -28,12 +29,47 @@ static inline void ls1012ardb_reset_phy(void)
 {
 #ifdef CONFIG_TARGET_LS1012ARDB
        /* Through reset IO expander reset both RGMII and SGMII PHYs */
+#if CONFIG_IS_ENABLED(DM_I2C)
+       struct udevice *dev;
+       int ret;
+
+       /*
+        * The I2C IO-expander PCAL9555A is mouted on I2C1 bus(bus number is 0).
+        */
+       ret = i2c_get_chip_for_busnum(0, I2C_MUX_IO2_ADDR,
+                                     1, &dev);
+       if (ret) {
+               printf("%s: Cannot find udev for a bus %d\n", __func__,
+                      0);
+               return;
+       }
+       /* Config port 0
+        * - config pin IOXP_RST_ETH1_B and IOXP_RST_ETH2_B
+        *   are enabled as an output.
+        */
+       dm_i2c_reg_write(dev, 6, __PHY_MASK);
+
+       /*
+        * Set port 0 output a value to reset ETH2 interface
+        * - pin IOXP_RST_ETH2_B output 0b0
+        */
+       dm_i2c_reg_write(dev, 2, __PHY_ETH2_MASK);
+       mdelay(10);
+       dm_i2c_reg_write(dev, 2, __PHY_ETH1_MASK);
+       /*
+        * Set port 0 output a value to reset ETH1 interface
+        * - pin IOXP_RST_ETH1_B output 0b0
+        */
+       mdelay(10);
+       dm_i2c_reg_write(dev, 2, 0xFF);
+#else
        i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
        i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
        mdelay(10);
        i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH1_MASK);
        mdelay(10);
        i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
+#endif
        mdelay(50);
 #endif
 }
@@ -77,7 +113,7 @@ int pfe_eth_board_init(struct udevice *dev)
                        /* MAC2 */
                        pfe_set_phy_address_mode(priv->gemac_port,
                                                 CONFIG_PFE_EMAC2_PHY_ADDR,
-                                                PHY_INTERFACE_MODE_RGMII_TXID);
+                                                PHY_INTERFACE_MODE_RGMII_ID);
                }
                break;
        case 0x2208:
@@ -85,12 +121,12 @@ int pfe_eth_board_init(struct udevice *dev)
                        /* MAC1 */
                        pfe_set_phy_address_mode(priv->gemac_port,
                                                 CONFIG_PFE_EMAC1_PHY_ADDR,
-                                                PHY_INTERFACE_MODE_SGMII_2500);
+                                                PHY_INTERFACE_MODE_2500BASEX);
                } else {
                        /* MAC2 */
                        pfe_set_phy_address_mode(priv->gemac_port,
                                                 CONFIG_PFE_EMAC2_PHY_ADDR,
-                                                PHY_INTERFACE_MODE_SGMII_2500);
+                                                PHY_INTERFACE_MODE_2500BASEX);
                }
                break;
        default:
@@ -124,12 +160,12 @@ static struct pfe_eth_pdata pfe_pdata1 = {
        },
 };
 
-U_BOOT_DEVICE(ls1012a_pfe0) = {
+U_BOOT_DRVINFO(ls1012a_pfe0) = {
        .name = "pfe_eth",
-       .platdata = &pfe_pdata0,
+       .plat = &pfe_pdata0,
 };
 
-U_BOOT_DEVICE(ls1012a_pfe1) = {
+U_BOOT_DRVINFO(ls1012a_pfe1) = {
        .name = "pfe_eth",
-       .platdata = &pfe_pdata1,
+       .plat = &pfe_pdata1,
 };