board: freescale: ls1012a: Enable secure DDR on LS1012A platforms

[platform/kernel/u-boot.git] / board / freescale / ls1012afrdm / ls1012afrdm.c

diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
index b03bdb8..c2432c3 100644 (file)
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -85,3 +85,32 @@ int ft_board_setup(void *blob, bd_t *bd)
 
        return 0;
 }
+
+void dram_init_banksize(void)
+{
+       /*
+        * gd->arch.secure_ram tracks the location of secure memory.
+        * It was set as if the memory starts from 0.
+        * The address needs to add the offset of its bank.
+        */
+       gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+       if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
+               gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
+               gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+               gd->bd->bi_dram[1].size = gd->ram_size -
+                       CONFIG_SYS_DDR_BLOCK1_SIZE;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+               gd->arch.secure_ram = gd->bd->bi_dram[1].start +
+                       gd->arch.secure_ram -
+                       CONFIG_SYS_DDR_BLOCK1_SIZE;
+               gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
+       } else {
+               gd->bd->bi_dram[0].size = gd->ram_size;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+               gd->arch.secure_ram = gd->bd->bi_dram[0].start +
+                       gd->arch.secure_ram;
+               gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
+       }
+}