layerscape: Disable CONFIG_FMAN_ENET on *aqds* platforms

[platform/kernel/u-boot.git] / board / freescale / corenet_ds / eth_superhydra.c

diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c
index 3f11f5f..55bac0f 100644 (file)
--- a/board/freescale/corenet_ds/eth_superhydra.c
+++ b/board/freescale/corenet_ds/eth_superhydra.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2009-2011 Freescale Semiconductor, Inc.
  * Author: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /*
@@ -49,6 +48,8 @@
  */
 
 #include <common.h>
+#include <log.h>
+#include <net.h>
 #include <netdev.h>
 #include <asm/fsl_serdes.h>
 #include <fm_eth.h>
@@ -316,6 +317,9 @@ void fdt_fixup_board_enet(void *fdt)
                        }
                        break;
                case PHY_INTERFACE_MODE_RGMII:
+               case PHY_INTERFACE_MODE_RGMII_TXID:
+               case PHY_INTERFACE_MODE_RGMII_RXID:
+               case PHY_INTERFACE_MODE_RGMII_ID:
                        fdt_status_okay_by_alias(fdt, "hydra_rg");
                        debug("Enabled MDIO node hydra_rg\n");
                        break;
@@ -352,6 +356,9 @@ void fdt_fixup_board_enet(void *fdt)
                        }
                        break;
                case PHY_INTERFACE_MODE_RGMII:
+               case PHY_INTERFACE_MODE_RGMII_TXID:
+               case PHY_INTERFACE_MODE_RGMII_RXID:
+               case PHY_INTERFACE_MODE_RGMII_ID:
                        fdt_status_okay_by_alias(fdt, "hydra_rg");
                        debug("Enabled MDIO node hydra_rg\n");
                        break;
@@ -414,7 +421,7 @@ void fdt_fixup_board_enet(void *fdt)
  * 0x36                |                 |                 |
  */
 
-int board_eth_init(bd_t *bis)
+int board_eth_init(struct bd_info *bis)
 {
 #ifdef CONFIG_FMAN_ENET
        struct fsl_pq_mdio_info dtsec_mdio_info;
@@ -556,6 +563,9 @@ int board_eth_init(bd_t *bis)
                        miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"));
                        break;
                case PHY_INTERFACE_MODE_RGMII:
+               case PHY_INTERFACE_MODE_RGMII_TXID:
+               case PHY_INTERFACE_MODE_RGMII_RXID:
+               case PHY_INTERFACE_MODE_RGMII_ID:
                        /*
                         * FM1 DTSEC5 is routed via EC1 to the first on-board
                         * RGMII port. FM2 DTSEC5 is routed via EC2 to the
@@ -573,7 +583,7 @@ int board_eth_init(bd_t *bis)
                        fm_info_set_mdio(i,
                                miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
                        break;
-               case PHY_INTERFACE_MODE_NONE:
+               case PHY_INTERFACE_MODE_NA:
                        fm_info_set_phy_address(i, 0);
                        break;
                default:
@@ -703,6 +713,9 @@ int board_eth_init(bd_t *bis)
 
                        break;
                case PHY_INTERFACE_MODE_RGMII:
+               case PHY_INTERFACE_MODE_RGMII_TXID:
+               case PHY_INTERFACE_MODE_RGMII_RXID:
+               case PHY_INTERFACE_MODE_RGMII_ID:
                        /*
                         * FM1 DTSEC5 is routed via EC1 to the first on-board
                         * RGMII port. FM2 DTSEC5 is routed via EC2 to the
@@ -720,7 +733,7 @@ int board_eth_init(bd_t *bis)
                        fm_info_set_mdio(i,
                        miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
                        break;
-               case PHY_INTERFACE_MODE_NONE:
+               case PHY_INTERFACE_MODE_NA:
                        fm_info_set_phy_address(i, 0);
                        break;
                default: