}
break;
case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_ID:
fdt_status_okay_by_alias(fdt, "hydra_rg");
debug("Enabled MDIO node hydra_rg\n");
break;
}
break;
case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_ID:
fdt_status_okay_by_alias(fdt, "hydra_rg");
debug("Enabled MDIO node hydra_rg\n");
break;
miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"));
break;
case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_ID:
/*
* FM1 DTSEC5 is routed via EC1 to the first on-board
* RGMII port. FM2 DTSEC5 is routed via EC2 to the
fm_info_set_mdio(i,
miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
break;
- case PHY_INTERFACE_MODE_NONE:
+ case PHY_INTERFACE_MODE_NA:
fm_info_set_phy_address(i, 0);
break;
default:
break;
case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_ID:
/*
* FM1 DTSEC5 is routed via EC1 to the first on-board
* RGMII port. FM2 DTSEC5 is routed via EC2 to the
fm_info_set_mdio(i,
miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
break;
- case PHY_INTERFACE_MODE_NONE:
+ case PHY_INTERFACE_MODE_NA:
fm_info_set_phy_address(i, 0);
break;
default: