Merge tag 'u-boot-atmel-fixes-2021.01-b' of https://gitlab.denx.de/u-boot/custodians...

[platform/kernel/u-boot.git] / board / freescale / corenet_ds / eth_p4080.c

diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c
index 597d0cb..df5a69b 100644 (file)
--- a/board/freescale/corenet_ds/eth_p4080.c
+++ b/board/freescale/corenet_ds/eth_p4080.c
@@ -1,18 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2009-2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <command.h>
+#include <fdt_support.h>
+#include <net.h>
 #include <netdev.h>
 #include <asm/mmu.h>
 #include <asm/processor.h>
 #include <asm/cache.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_portals.h>
 #include <asm/fsl_liodn.h>
@@ -21,10 +22,11 @@
 #include <fsl_mdio.h>
 #include <miiphy.h>
 #include <phy.h>
+#include <linux/delay.h>
 
 #include "../common/ngpixis.h"
 #include "../common/fman.h"
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 
 #define EMI_NONE       0xffffffff
 #define EMI_MASK       0xf0000000
@@ -37,6 +39,9 @@
 #define EMI1_MASK      0xc0000000
 #define EMI2_MASK      0x30000000
 
+#define PHY_BASE_ADDR  0x00
+#define PHY_BASE_ADDR_SLOT5    0x10
+
 static int mdio_mux[NUM_FM_PORTS];
 
 static char *mdio_names[16] = {
@@ -283,13 +288,14 @@ void fdt_fixup_board_enet(void *fdt)
        }
 }
 
-int board_eth_init(bd_t *bis)
+int board_eth_init(struct bd_info *bis)
 {
 #ifdef CONFIG_FMAN_ENET
        ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
        int i;
        struct fsl_pq_mdio_info dtsec_mdio_info;
        struct tgec_mdio_info tgec_mdio_info;
+       struct mii_dev *bus;
 
        /* Initialize the mdio_mux array so we can recognize empty elements */
        for (i = 0; i < NUM_FM_PORTS; i++)
@@ -361,6 +367,9 @@ int board_eth_init(bd_t *bis)
                        };
                        break;
                case PHY_INTERFACE_MODE_RGMII:
+               case PHY_INTERFACE_MODE_RGMII_TXID:
+               case PHY_INTERFACE_MODE_RGMII_RXID:
+               case PHY_INTERFACE_MODE_RGMII_ID:
                        fm_info_set_phy_address(i, 0);
                        mdio_mux[i] = EMI1_RGMII;
                        fm_info_set_mdio(i,
@@ -370,6 +379,9 @@ int board_eth_init(bd_t *bis)
                        break;
                }
        }
+       bus = mii_dev_for_muxval(EMI1_SLOT5);
+       set_sgmii_phy(bus, FM1_DTSEC1,
+                     CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR_SLOT5);
 
        for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
                int idx = i - FM1_10GEC1, lane, slot;
@@ -425,6 +437,9 @@ int board_eth_init(bd_t *bis)
                        };
                        break;
                case PHY_INTERFACE_MODE_RGMII:
+               case PHY_INTERFACE_MODE_RGMII_TXID:
+               case PHY_INTERFACE_MODE_RGMII_RXID:
+               case PHY_INTERFACE_MODE_RGMII_ID:
                        fm_info_set_phy_address(i, 0);
                        mdio_mux[i] = EMI1_RGMII;
                        fm_info_set_mdio(i,
@@ -435,6 +450,11 @@ int board_eth_init(bd_t *bis)
                }
        }
 
+       bus = mii_dev_for_muxval(EMI1_SLOT3);
+       set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR);
+       bus = mii_dev_for_muxval(EMI1_SLOT4);
+       set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR);
+
        for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
                int idx = i - FM2_10GEC1, lane, slot;
                switch (fm_info_get_enet_if(i)) {