Merge tag 'u-boot-atmel-fixes-2021.01-b' of https://gitlab.denx.de/u-boot/custodians...

[platform/kernel/u-boot.git] / board / freescale / corenet_ds / eth_hydra.c

diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c
index a594efc..6500c2f 100644 (file)
--- a/board/freescale/corenet_ds/eth_hydra.c
+++ b/board/freescale/corenet_ds/eth_hydra.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2009-2011 Freescale Semiconductor, Inc.
  * Author: Timur Tabi <timur@freescale.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /*
@@ -49,20 +48,21 @@
  */
 
 #include <common.h>
+#include <net.h>
 #include <netdev.h>
 #include <asm/fsl_serdes.h>
 #include <fm_eth.h>
 #include <fsl_mdio.h>
 #include <malloc.h>
 #include <fdt_support.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 
 #include "../common/ngpixis.h"
 #include "../common/fman.h"
 
 #ifdef CONFIG_FMAN_ENET
 
-#define BRDCFG1_EMI1_SEL_MASK  0x70
+#define BRDCFG1_EMI1_SEL_MASK  0x78
 #define BRDCFG1_EMI1_SEL_SLOT1 0x10
 #define BRDCFG1_EMI1_SEL_SLOT2 0x20
 #define BRDCFG1_EMI1_SEL_SLOT5 0x30
@@ -76,6 +76,8 @@
 
 #define BRDCFG2_REG_GPIO_SEL   0x20
 
+#define PHY_BASE_ADDR          0x00
+
 /*
  * BRDCFG1 mask and value for each MAC
  *
@@ -168,7 +170,7 @@ static int hydra_mdio_init(char *realbusname, char *fakebusname)
        bus->read = hydra_mdio_read;
        bus->write = hydra_mdio_write;
        bus->reset = hydra_mdio_reset;
-       sprintf(bus->name, fakebusname);
+       strcpy(bus->name, fakebusname);
 
        hmdio->realbus = miiphy_get_dev_by_name(realbusname);
 
@@ -200,6 +202,8 @@ static void fdt_set_mdio_mux(void *fdt, const char *alias, u32 mux)
        if (!path)
                path = alias;
 
+       do_fixup_by_path(fdt, path, "reg",
+                        &mux, sizeof(mux), 1);
        do_fixup_by_path(fdt, path, "fsl,hydra-mdio-muxval",
                         &mux, sizeof(mux), 1);
 }
@@ -248,11 +252,12 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
                return;
        }
 
-       if (mux == BRDCFG1_EMI1_SEL_RGMII) {
+       if (mux == (BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN)) {
                /* RGMII */
                /* The RGMII PHY is identified by the MAC connected to it */
                sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC4 ? 0 : 1);
                fdt_set_phy_handle(fdt, compat, addr, phy);
+               return;
        }
 
        /* If it's not RGMII or XGMII, it must be SGMII */
@@ -345,6 +350,9 @@ void fdt_fixup_board_enet(void *fdt)
                        }
                        break;
                case PHY_INTERFACE_MODE_RGMII:
+               case PHY_INTERFACE_MODE_RGMII_TXID:
+               case PHY_INTERFACE_MODE_RGMII_RXID:
+               case PHY_INTERFACE_MODE_RGMII_ID:
                        fdt_status_okay_by_alias(fdt, "emi1_rgmii");
                        break;
                default:
@@ -358,13 +366,14 @@ void fdt_fixup_board_enet(void *fdt)
 #endif
 }
 
-int board_eth_init(bd_t *bis)
+int board_eth_init(struct bd_info *bis)
 {
 #ifdef CONFIG_FMAN_ENET
        struct fsl_pq_mdio_info dtsec_mdio_info;
        struct tgec_mdio_info tgec_mdio_info;
        unsigned int i, slot;
        int lane;
+       struct mii_dev *bus;
 
        printf("Initializing Fman\n");
 
@@ -443,6 +452,9 @@ int board_eth_init(bd_t *bis)
                                miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"));
                        break;
                case PHY_INTERFACE_MODE_RGMII:
+               case PHY_INTERFACE_MODE_RGMII_TXID:
+               case PHY_INTERFACE_MODE_RGMII_RXID:
+               case PHY_INTERFACE_MODE_RGMII_ID:
                        /*
                         * If DTSEC4 is RGMII, then it's routed via via EC1 to
                         * the first on-board RGMII port.  If DTSEC5 is RGMII,
@@ -470,6 +482,9 @@ int board_eth_init(bd_t *bis)
                }
        }
 
+       bus = miiphy_get_dev_by_name("HYDRA_SGMII_MDIO");
+       set_sgmii_phy(bus, FM1_DTSEC1, CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR);
+
        /*
         * For 10G, we only support one XAUI card per Fman.  If present, then we
         * force its routing and never touch those bits again, which removes the